linux-kernel - Re: [PATCH v39 01/24] x86/cpufeatures: x86/msr: Add Intel SGX hardware bits

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Message-ID: <20201019174928.GA22358@linux.intel.com>
Date:   Mon, 19 Oct 2020 10:49:28 -0700
From:   Sean Christopherson <sean.j.christopherson@...el.com>
To:     Dave Hansen <dave.hansen@...el.com>
Cc:     Jarkko Sakkinen <jarkko.sakkinen@...ux.intel.com>, x86@...nel.org,
        linux-sgx@...r.kernel.org, linux-kernel@...r.kernel.org,
        Borislav Petkov <bp@...en8.de>,
        Jethro Beekman <jethro@...tanix.com>,
        Darren Kenny <darren.kenny@...cle.com>,
        akpm@...ux-foundation.org, andriy.shevchenko@...ux.intel.com,
        asapek@...gle.com, cedric.xing@...el.com, chenalexchen@...gle.com,
        conradparker@...gle.com, cyhanish@...gle.com,
        haitao.huang@...el.com, kai.huang@...el.com, kai.svahn@...el.com,
        kmoy@...gle.com, ludloff@...gle.com, luto@...nel.org,
        nhorman@...hat.com, npmccallum@...hat.com, puiterwijk@...hat.com,
        rientjes@...gle.com, tglx@...utronix.de, yaozhangx@...gle.com,
        mikko.ylinen@...el.com
Subject: Re: [PATCH v39 01/24] x86/cpufeatures: x86/msr: Add Intel SGX
 hardware bits

On Mon, Oct 19, 2020 at 07:10:58AM -0700, Dave Hansen wrote:
> On 10/2/20 9:50 PM, Jarkko Sakkinen wrote:
> > 
> > Add X86_FEATURE_SGX1 and X86_FEATURE_SGX2 from CPUID.(EAX=12H, ECX=0),
> > which describe the level of SGX support available [1].
> 
> The SDM says there are 6 leaf functions added with SGX2 (SDM Vol 3D
> Table 36-2):
> 
> ENCLS[EAUG]
> ENCLS[EMODPR]
> ENCLS[EMODT]
> ENCLU[EACCEPT]
> ENCLU[EMODPE]
> ENCLU[EACCEPTCOPY]
> 
> But I don't see *ANY* of those in use in this patch set.  I know we
> added a bunch of infrastructure around mitigating if EMODPE got *used*,
> but does the kernel need to change its behavior if SGX1 vs. SGX2 is
> supported?
> 
> BTW, the SG2 bit is defined:
> 
> 	Bit 01: SGX2. If 1, Indicates Intel SGX supports the collection
> 	of SGX2 leaf functions.
> 
> which makes me think it's for leaf functions only.

As mentioned in the other thread, SGX1 hardware takes an erratum on the #PF
behavior of the EPCM, i.e. on SGX2+, EPCM violations generate #PF with
PFEC.SGX=1, whereas SGX1 hardware will #GP.