linux-kernel - Re: [PATCH v39 05/24] x86/sgx: Add wrappers for ENCLS leaf functions

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Message-ID: <20201019175353.GB22358@linux.intel.com>
Date:   Mon, 19 Oct 2020 10:53:53 -0700
From:   Sean Christopherson <sean.j.christopherson@...el.com>
To:     Dave Hansen <dave.hansen@...el.com>
Cc:     Jarkko Sakkinen <jarkko.sakkinen@...ux.intel.com>, x86@...nel.org,
        linux-sgx@...r.kernel.org, linux-kernel@...r.kernel.org,
        Jethro Beekman <jethro@...tanix.com>,
        Darren Kenny <darren.kenny@...cle.com>,
        akpm@...ux-foundation.org, andriy.shevchenko@...ux.intel.com,
        asapek@...gle.com, bp@...en8.de, cedric.xing@...el.com,
        chenalexchen@...gle.com, conradparker@...gle.com,
        cyhanish@...gle.com, haitao.huang@...el.com, kai.huang@...el.com,
        kai.svahn@...el.com, kmoy@...gle.com, ludloff@...gle.com,
        luto@...nel.org, nhorman@...hat.com, npmccallum@...hat.com,
        puiterwijk@...hat.com, rientjes@...gle.com, tglx@...utronix.de,
        yaozhangx@...gle.com, mikko.ylinen@...el.com
Subject: Re: [PATCH v39 05/24] x86/sgx: Add wrappers for ENCLS leaf functions

On Mon, Oct 19, 2020 at 10:48:35AM -0700, Dave Hansen wrote:
> On 10/19/20 10:38 AM, Sean Christopherson wrote:
> >>> +static inline bool encls_failed(int ret)
> >>> +{
> >>> +	int epcm_trapnr;
> >>> +
> >>> +	if (boot_cpu_has(X86_FEATURE_SGX2))
> >>> +		epcm_trapnr = X86_TRAP_PF;
> >>> +	else
> >>> +		epcm_trapnr = X86_TRAP_GP;
> >> So, the SDM makes it sound like the only thing that changes from
> >> SGX1->SGX2 is the ENCLS leafs supported.  Since the kernel doesn't use
> >> any SGX2 leaf functions, this would imply there is some other
> >> architecture change which is visible.  *But* I don't see any evidence of
> >> this in the SDM, at least from a quick scan.
> >>
> >> Why is this here?
> > SGX1 CPUs take an erratum on the #PF behavior, e.g. "KBW90 Violation of Intel
> > SGX Access-Control Requirements Produce #GP Instead of #PF".
> > 
> > https://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/xeon-e3-1200v6-spec-update.pdf
> 
> OK, but that's only for "Intel ® Xeon ® E3-1200 v6 Processor Family",
> specifically stepping B-0.  That's far from a broad erratum.  I *see* it
> in other errata lists, but I still think this is too broad.
> 
> Also, what if a hypervisor masks the SGX2 cpuid bit on SGX2-capable
> hardware?  Won't the hardware still exhibit the erratum?
> 
> I don't think we can control model-specific errata behavior with an
> architectural CPUID bit.

Hmm, true.  Checking for #PF _or_ #GP on SGX1 CPUs would be my first choice.
ENCLS #GPs for other reasons, most of which would indicate a kernel bug.  It'd
be nice to limit the "#GP is expected, sort of" behavior to CPUs that might be
affected by an erratum.