linux-kernel - Re: [PATCH] clk: exynos7: Mark aclk_fsys1

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Message-ID: <56fb4ede-e81a-5721-1927-77f2410d5885@samsung.com>
Date:   Mon, 26 Oct 2020 14:46:24 +0900
From:   Chanwoo Choi <cw00.choi@...sung.com>
To:     Paweł Chmiel <pawel.mikolaj.chmiel@...il.com>,
        kgene@...nel.org, krzk@...nel.org, mturquette@...libre.com,
        sboyd@...nel.org
Cc:     s.nawrocki@...sung.com, tomasz.figa@...il.com,
        linux-samsung-soc@...r.kernel.org, linux-clk@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH] clk: exynos7: Mark aclk_fsys1_200 as critical

Hi Paweł Chmiel,

On 10/25/20 12:43 AM, Paweł Chmiel wrote:
> This clock must be always enabled to allow access to any registers in
> fsys1 CMU. Until proper solution based on runtime PM is applied
> (similar to what was done for Exynos5433), mark that clock as critical
> so it won't be disabled.
> 
> It was observed on Samsung Galaxy S6 device (based on Exynos7420), where
> UFS module is probed before pmic used to power that device.
> In this case defer probe was happening and that clock was disabled by
> UFS driver, causing whole boot to hang on next CMU access.
> 
> Signed-off-by: Paweł Chmiel <pawel.mikolaj.chmiel@...il.com>
> ---
>  drivers/clk/samsung/clk-exynos7.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c
> index c1ff715e960c..1048d83f097b 100644
> --- a/drivers/clk/samsung/clk-exynos7.c
> +++ b/drivers/clk/samsung/clk-exynos7.c
> @@ -538,7 +538,8 @@ static const struct samsung_gate_clock top1_gate_clks[] __initconst = {
>  		ENABLE_ACLK_TOP13, 28, CLK_SET_RATE_PARENT |
>  		CLK_IS_CRITICAL, 0),
>  	GATE(CLK_ACLK_FSYS1_200, "aclk_fsys1_200", "dout_aclk_fsys1_200",
> -		ENABLE_ACLK_TOP13, 24, CLK_SET_RATE_PARENT, 0),
> +		ENABLE_ACLK_TOP13, 24, CLK_SET_RATE_PARENT |
> +		CLK_IS_CRITICAL, 0),

As you commented, in order to keep the always on state,
we can use CLK_IS_CRITICAL. Instead, you can enable the specific clock
with detailed comment on clk-exynos7.c as following merged patches[1][2]:
[1] 67f96ff7c8f0 ("clk: samsung: exynos5420: Keep top G3D clocks enabled")
[2] 0212a0483b0a ("clk: samsung: Keep top BPLL mux on Exynos542x enabled")

The patches[1][2] enable the clock with clk_prepare_enable()
instead of adding CLK_IS_CRITICAL. You can refer to it.

>  
>  	GATE(CLK_SCLK_PHY_FSYS1_26M, "sclk_phy_fsys1_26m",
>  		"dout_sclk_phy_fsys1_26m", ENABLE_SCLK_TOP1_FSYS11,
> 


-- 
Best Regards,
Chanwoo Choi
Samsung Electronics