linux-kernel - RE: [RESEND 01/11] irqchip: ls-extirq: Add LS1043A, LS1088A external interrupt

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Date:   Tue, 27 Oct 2020 03:25:53 +0000
From:   "Biwen Li (OSS)" <biwen.li@....nxp.com>
To:     Rasmus Villemoes <linux@...musvillemoes.dk>,
        Marc Zyngier <maz@...nel.org>,
        "Biwen Li (OSS)" <biwen.li@....nxp.com>
CC:     "shawnguo@...nel.org" <shawnguo@...nel.org>,
        "robh+dt@...nel.org" <robh+dt@...nel.org>,
        "mark.rutland@....com" <mark.rutland@....com>,
        Leo Li <leoyang.li@....com>, "Z.q. Hou" <zhiqiang.hou@....com>,
        "tglx@...utronix.de" <tglx@...utronix.de>,
        "jason@...edaemon.net" <jason@...edaemon.net>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        Jiafei Pan <jiafei.pan@....com>,
        Xiaobo Xie <xiaobo.xie@....com>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>
Subject: RE: [RESEND 01/11] irqchip: ls-extirq: Add LS1043A, LS1088A external
 interrupt

> Subject: Re: [RESEND 01/11] irqchip: ls-extirq: Add LS1043A, LS1088A external
> interrupt
> 
> On 26/10/2020 09.44, Marc Zyngier wrote:
> > On 2020-10-26 08:01, Biwen Li wrote:
> >> From: Hou Zhiqiang <Zhiqiang.Hou@....com>
> >>
> >> Add an new IRQ chip declaration for LS1043A and LS1088A
> >> - compatible "fsl,ls1043a-extirq" for LS1043A, LS1046A
> >> - compatible "fsl,ls1088a-extirq" for LS1088A, LS208xA, LX216xA
> >
> > Three things:
> > - This commit message doesn't describe the bit_reverse change
> 
> Yeah, please elaborate on that, as the RM for 1043 or 1046 doesn't mention
> anything about bit reversal for the scfg registers - they don't seem to have the
> utter nonsense that is SCFG_SCFGREVCR, but perhaps, instead of removing it,
> that has just become a hard-coded part of the IP.
Yeah, you are right, I will update it in v2.
> 
> Also, IANAL etc., but
> 
> >> +// Copyright 2019-2020 NXP
> 
> really? Seems to be a bit of a stretch.
> 
> At the very least, cc'ing the original author and only person to ever touch that
> file would have been appreciated.
Okay, it's my fault, I will update it, thanks.
> 
> Rasmus