linux-kernel - Re: [RFC PATCH 3/3] RISC-V: Enable Microchip PolarFire ICICLE SoC

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Date:   Fri, 30 Oct 2020 21:21:37 +0000
From:   Ben Dooks <ben.dooks@...ethink.co.uk>
To:     Anup Patel <anup@...infault.org>, Atish Patra <atish.patra@....com>
Cc:     devicetree@...r.kernel.org, Albert Ou <aou@...s.berkeley.edu>,
        Cyril.Jean@...rochip.com,
        Daire McNamara <daire.mcnamara@...rochip.com>,
        Anup Patel <anup.patel@....com>,
        "linux-kernel@...r.kernel.org List" <linux-kernel@...r.kernel.org>,
        Rob Herring <robh+dt@...nel.org>,
        Alistair Francis <alistair.francis@....com>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Palmer Dabbelt <palmer@...belt.com>,
        linux-riscv <linux-riscv@...ts.infradead.org>,
        Padmarao Begari <padmarao.begari@...rochip.com>
Subject: Re: [RFC PATCH 3/3] RISC-V: Enable Microchip PolarFire ICICLE SoC

On 30/10/2020 09:09, Anup Patel wrote:
> On Thu, Oct 29, 2020 at 4:58 AM Atish Patra <atish.patra@....com> wrote:
>>
>> Enable Microchip PolarFire ICICLE soc config in defconfig.
>> It allows the default upstream kernel to boot on PolarFire ICICLE board.
>>
>> Signed-off-by: Atish Patra <atish.patra@....com>
>> ---

Is there going to be a git tree with all the necessary support for the
polarfire/icicle boards? I so far have updated yocto patches, a rebase
to v5.9 and the v17 PCIe patches (which still don't work for us)

-- 
Ben Dooks				http://www.codethink.co.uk/
Senior Engineer				Codethink - Providing Genius

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