linux-kernel - Re: [PATCH v2] clk: renesas: r8a774c0: Add RPC clocks

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Message-ID: <CAMuHMdVPHhot+noBYwqfCtwYzKJD4hkwjBk_gwN4pDR0agwipg@mail.gmail.com>
Date:   Fri, 30 Oct 2020 08:55:21 +0100
From:   Geert Uytterhoeven <geert@...ux-m68k.org>
To:     Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Cc:     Michael Turquette <mturquette@...libre.com>,
        Stephen Boyd <sboyd@...nel.org>,
        Linux-Renesas <linux-renesas-soc@...r.kernel.org>,
        linux-clk <linux-clk@...r.kernel.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        Biju Das <biju.das.jz@...renesas.com>,
        Prabhakar <prabhakar.csengg@...il.com>
Subject: Re: [PATCH v2] clk: renesas: r8a774c0: Add RPC clocks

Hi Prabhakar,

On Thu, Oct 29, 2020 at 3:28 PM Geert Uytterhoeven <geert@...ux-m68k.org> wrote:
> On Thu, Oct 29, 2020 at 11:55 AM Lad Prabhakar
> <prabhakar.mahadev-lad.rj@...renesas.com> wrote:
> > Describe the RPCSRC internal clock and the RPC[D2] clocks derived from it,
> > as well as the RPC-IF module clock, in the RZ/G2E (R8A774C0) CPG/MSSR
> > driver.

> > +               if (e3_rpcsrc_parent) {
> > +                       parent = clks[core->parent >> 16];
> > +                       if (IS_ERR(parent))
> > +                               return ERR_CAST(parent);
> > +               }
> > +
> > +               return clk_register_divider_table(NULL, core->name,
> > +                                                 __clk_get_name(parent), 0,
> > +                                                 base + CPG_RPCCKCR, 3, 2, 0,
> > +                                                 e3_rpcsrc_parent ?
> > +                                                 cpg_rpcsrc_e3_pll1_div_table :
> > +                                                 cpg_rpcsrc_e3_pll0_div_table,
> > +                                                 &cpg_lock);
> > +
>
> So you want to keep the parent clock selection fixed, but still allow
> the system to change the divider?
> Why not support changing the parent too, by modeling this as a composite
> clock consisting of a mux and a divider?

To clarify: basically you have two options here:
  1. Model this clock as a non-mutable clock, based on the register settings
     at the time the kernel boots.  I.e. register it as a fixed-divider clock.
     This is how we handle the PLLx clocks.
  2. Model this clock as a fully-programmable clock.  I.e. implement both
     dynamic parent selection and dynamic divider selection.

You have picked something in between ;-)

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds