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Message-ID: <CADnq5_Nc_wPfB6Jwzdmc00g_QKLLqf71vu6YO-3oqY8piFMoPw@mail.gmail.com>
Date:   Mon, 2 Nov 2020 14:55:21 -0500
From:   Alex Deucher <alexdeucher@...il.com>
To:     Deepak R Varma <mh12gx2825@...il.com>
Cc:     Alex Deucher <alexander.deucher@....com>,
        Christian König <christian.koenig@....com>,
        David Airlie <airlied@...ux.ie>,
        Daniel Vetter <daniel@...ll.ch>,
        amd-gfx list <amd-gfx@...ts.freedesktop.org>,
        Maling list - DRI developers 
        <dri-devel@...ts.freedesktop.org>,
        LKML <linux-kernel@...r.kernel.org>,
        Melissa Wen <melissa.srw@...il.com>,
        Greg KH <gregkh@...uxfoundation.org>,
        Daniel Vetter <daniel.vetter@...ll.ch>
Subject: Re: [PATCH 6/6] drm/amdgpu: use "*" adjacent to data name

Applied the series.  Thanks!

Alex

On Mon, Nov 2, 2020 at 2:41 PM Deepak R Varma <mh12gx2825@...il.com> wrote:
>
> When declaring pointer data, the "*" symbol should be used adjacent to
> the data name as per the coding standards. This resolves following
> issues reported by checkpatch script:
>         ERROR: "foo *   bar" should be "foo *bar"
>         ERROR: "foo * bar" should be "foo *bar"
>         ERROR: "foo*            bar" should be "foo *bar"
>         ERROR: "(foo*)" should be "(foo *)"
>
> Signed-off-by: Deepak R Varma <mh12gx2825@...il.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/atom.c         | 16 ++++++++--------
>  drivers/gpu/drm/amd/amdgpu/atombios_i2c.c |  2 +-
>  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c     |  4 ++--
>  drivers/gpu/drm/amd/amdgpu/mes_v10_1.c    |  2 +-
>  drivers/gpu/drm/amd/amdgpu/psp_v11_0.c    |  2 +-
>  5 files changed, 13 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/atom.c b/drivers/gpu/drm/amd/amdgpu/atom.c
> index 46c00ee580b1..515890f4f5a0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/atom.c
> +++ b/drivers/gpu/drm/amd/amdgpu/atom.c
> @@ -67,8 +67,8 @@ typedef struct {
>  } atom_exec_context;
>
>  int amdgpu_atom_debug;
> -static int amdgpu_atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t * params);
> -int amdgpu_atom_execute_table(struct atom_context *ctx, int index, uint32_t * params);
> +static int amdgpu_atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t *params);
> +int amdgpu_atom_execute_table(struct atom_context *ctx, int index, uint32_t *params);
>
>  static uint32_t atom_arg_mask[8] =
>         { 0xFFFFFFFF, 0xFFFF, 0xFFFF00, 0xFFFF0000, 0xFF, 0xFF00, 0xFF0000,
> @@ -1201,7 +1201,7 @@ static struct {
>         atom_op_div32, ATOM_ARG_WS},
>  };
>
> -static int amdgpu_atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t * params)
> +static int amdgpu_atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t *params)
>  {
>         int base = CU16(ctx->cmd_table + 4 + 2 * index);
>         int len, ws, ps, ptr;
> @@ -1262,7 +1262,7 @@ static int amdgpu_atom_execute_table_locked(struct atom_context *ctx, int index,
>         return ret;
>  }
>
> -int amdgpu_atom_execute_table(struct atom_context *ctx, int index, uint32_t * params)
> +int amdgpu_atom_execute_table(struct atom_context *ctx, int index, uint32_t *params)
>  {
>         int r;
>
> @@ -1388,8 +1388,8 @@ void amdgpu_atom_destroy(struct atom_context *ctx)
>  }
>
>  bool amdgpu_atom_parse_data_header(struct atom_context *ctx, int index,
> -                           uint16_t * size, uint8_t * frev, uint8_t * crev,
> -                           uint16_t * data_start)
> +                           uint16_t *size, uint8_t *frev, uint8_t *crev,
> +                           uint16_t *data_start)
>  {
>         int offset = index * 2 + 4;
>         int idx = CU16(ctx->data_table + offset);
> @@ -1408,8 +1408,8 @@ bool amdgpu_atom_parse_data_header(struct atom_context *ctx, int index,
>         return true;
>  }
>
> -bool amdgpu_atom_parse_cmd_header(struct atom_context *ctx, int index, uint8_t * frev,
> -                          uint8_t * crev)
> +bool amdgpu_atom_parse_cmd_header(struct atom_context *ctx, int index, uint8_t *frev,
> +                          uint8_t *crev)
>  {
>         int offset = index * 2 + 4;
>         int idx = CU16(ctx->cmd_table + offset);
> diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_i2c.c b/drivers/gpu/drm/amd/amdgpu/atombios_i2c.c
> index 09a538465ffd..af0335535f82 100644
> --- a/drivers/gpu/drm/amd/amdgpu/atombios_i2c.c
> +++ b/drivers/gpu/drm/amd/amdgpu/atombios_i2c.c
> @@ -159,7 +159,7 @@ u32 amdgpu_atombios_i2c_func(struct i2c_adapter *adap)
>         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
>  }
>
> -void amdgpu_atombios_i2c_channel_trans(struct amdgpu_device* adev, u8 slave_addr, u8 line_number, u8 offset, u8 data)
> +void amdgpu_atombios_i2c_channel_trans(struct amdgpu_device *adev, u8 slave_addr, u8 line_number, u8 offset, u8 data)
>  {
>         PROCESS_I2C_CHANNEL_TRANSACTION_PS_ALLOCATION args;
>         int index = GetIndexIntoMasterTable(COMMAND, ProcessI2cChannelTransaction);
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 48f98c750956..e96ab5325af5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -5167,7 +5167,7 @@ static void gfx_v9_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
>
>         if (ring->use_doorbell) {
>                 /* XXX check if swapping is necessary on BE */
> -               atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr);
> +               atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
>                 WDOORBELL64(ring->doorbell_index, ring->wptr);
>         } else {
>                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
> @@ -5353,7 +5353,7 @@ static void gfx_v9_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
>
>         /* XXX check if swapping is necessary on BE */
>         if (ring->use_doorbell) {
> -               atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr);
> +               atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
>                 WDOORBELL64(ring->doorbell_index, ring->wptr);
>         } else{
>                 BUG(); /* only DOORBELL method supported on gfx9 now */
> diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
> index 1c22d8393b21..985e454463e1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
> @@ -46,7 +46,7 @@ static void mes_v10_1_ring_set_wptr(struct amdgpu_ring *ring)
>         struct amdgpu_device *adev = ring->adev;
>
>         if (ring->use_doorbell) {
> -               atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs],
> +               atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs],
>                              ring->wptr);
>                 WDOORBELL64(ring->doorbell_index, ring->wptr);
>         } else {
> diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
> index 6c5d9612abcb..d521ca0f3afa 100644
> --- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
> @@ -615,7 +615,7 @@ static int psp_v11_0_memory_training_send_msg(struct psp_context *psp, int msg)
>  static int psp_v11_0_memory_training(struct psp_context *psp, uint32_t ops)
>  {
>         struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
> -       uint32_t *pcache = (uint32_t*)ctx->sys_cache;
> +       uint32_t *pcache = (uint32_t *)ctx->sys_cache;
>         struct amdgpu_device *adev = psp->adev;
>         uint32_t p2c_header[4];
>         uint32_t sz;
> --
> 2.25.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@...ts.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx

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