linux-kernel - Re: [PATCH v6 3/6] spi: cadence-quadspi: Add multi-chipselect support for Intel LGM SoC

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Message-ID: <CACRpkdZnAfogewQt83wDMmkhb4kZD=qdbq26nHcam3401WGiOA@mail.gmail.com>
Date:   Thu, 5 Nov 2020 08:11:41 +0100
From:   Linus Walleij <linus.walleij@...aro.org>
To:     "Ramuthevar,Vadivel MuruganX" 
        <vadivel.muruganx.ramuthevar@...ux.intel.com>
Cc:     Mark Brown <broonie@...nel.org>, Vignesh R <vigneshr@...com>,
        Tudor Ambarus <tudor.ambarus@...rochip.com>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        linux-spi <linux-spi@...r.kernel.org>,
        Rob Herring <robh+dt@...nel.org>,
        "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
        <devicetree@...r.kernel.org>,
        Miquèl Raynal <miquel.raynal@...tlin.com>,
        Simon Goldschmidt <simon.k.r.goldschmidt@...il.com>,
        Dinh Nguyen <dinguyen@...nel.org>,
        Richard Weinberger <richard@....at>, cheol.yong.kim@...el.com,
        qi-ming.wu@...el.com
Subject: Re: [PATCH v6 3/6] spi: cadence-quadspi: Add multi-chipselect support
 for Intel LGM SoC

On Fri, Oct 30, 2020 at 6:32 AM Ramuthevar,Vadivel MuruganX
<vadivel.muruganx.ramuthevar@...ux.intel.com> wrote:

> +       ddata  = of_device_get_match_data(dev);
> +       if (ddata->hwcaps_mask & CQSPI_SUPPORTS_MULTI_CHIPSELECT) {
> +               if (of_property_read_u32(np, "num-chipselect",

The standard SPI bindings in spi-controller.yaml already has a binding
for this "num-cs" so please use that. It is also what your device tree
binding is referencing, so if you were using "num-chipselect" the
YAML check should give a warning?

Yours,
Linus Walleij