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Message-ID: <5a4f6085-0408-d5e5-5f40-efc7814cbe42@linux.intel.com>
Date: Fri, 6 Nov 2020 12:33:06 +0800
From: "Ramuthevar, Vadivel MuruganX"
<vadivel.muruganx.ramuthevar@...ux.intel.com>
To: Linus Walleij <linus.walleij@...aro.org>
Cc: Mark Brown <broonie@...nel.org>, Vignesh R <vigneshr@...com>,
Tudor Ambarus <tudor.ambarus@...rochip.com>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
linux-spi <linux-spi@...r.kernel.org>,
Rob Herring <robh+dt@...nel.org>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@...r.kernel.org>,
Miquèl Raynal <miquel.raynal@...tlin.com>,
Simon Goldschmidt <simon.k.r.goldschmidt@...il.com>,
Dinh Nguyen <dinguyen@...nel.org>,
Richard Weinberger <richard@....at>, cheol.yong.kim@...el.com,
qi-ming.wu@...el.com
Subject: Re: [PATCH v6 3/6] spi: cadence-quadspi: Add multi-chipselect support
for Intel LGM SoC
Hi Linus,
Thank you for the review comments...
On 5/11/2020 3:11 pm, Linus Walleij wrote:
> On Fri, Oct 30, 2020 at 6:32 AM Ramuthevar,Vadivel MuruganX
> <vadivel.muruganx.ramuthevar@...ux.intel.com> wrote:
>
>> + ddata = of_device_get_match_data(dev);
>> + if (ddata->hwcaps_mask & CQSPI_SUPPORTS_MULTI_CHIPSELECT) {
>> + if (of_property_read_u32(np, "num-chipselect",
>
> The standard SPI bindings in spi-controller.yaml already has a binding
> for this "num-cs" so please use that. It is also what your device tree
> binding is referencing,
yes, you are point is valid, I will use that.
so if you were using "num-chipselect" the
> YAML check should give a warning?
In the example, I just converted from existing txt -to- yaml that's
why I didnt face any problem.
Regards
Vadivel
>
> Yours,
> Linus Walleij
>
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