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Date: Fri, 13 Nov 2020 08:57:41 -0400 From: Jason Gunthorpe <jgg@...dia.com> To: "Tian, Kevin" <kevin.tian@...el.com> CC: Thomas Gleixner <tglx@...utronix.de>, "Wilk, Konrad" <konrad.wilk@...cle.com>, "Raj, Ashok" <ashok.raj@...el.com>, "Williams, Dan J" <dan.j.williams@...el.com>, "Jiang, Dave" <dave.jiang@...el.com>, "Bjorn Helgaas" <helgaas@...nel.org>, "vkoul@...nel.org" <vkoul@...nel.org>, "Dey, Megha" <megha.dey@...el.com>, "maz@...nel.org" <maz@...nel.org>, "bhelgaas@...gle.com" <bhelgaas@...gle.com>, "alex.williamson@...hat.com" <alex.williamson@...hat.com>, "Pan, Jacob jun" <jacob.jun.pan@...el.com>, "Liu, Yi L" <yi.l.liu@...el.com>, "Lu, Baolu" <baolu.lu@...el.com>, "Kumar, Sanjay K" <sanjay.k.kumar@...el.com>, "Luck, Tony" <tony.luck@...el.com>, "kwankhede@...dia.com" <kwankhede@...dia.com>, "eric.auger@...hat.com" <eric.auger@...hat.com>, "parav@...lanox.com" <parav@...lanox.com>, "rafael@...nel.org" <rafael@...nel.org>, "netanelg@...lanox.com" <netanelg@...lanox.com>, "shahafs@...lanox.com" <shahafs@...lanox.com>, "yan.y.zhao@...ux.intel.com" <yan.y.zhao@...ux.intel.com>, "pbonzini@...hat.com" <pbonzini@...hat.com>, "Ortiz, Samuel" <samuel.ortiz@...el.com>, "Hossain, Mona" <mona.hossain@...el.com>, "dmaengine@...r.kernel.org" <dmaengine@...r.kernel.org>, "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>, "linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>, "kvm@...r.kernel.org" <kvm@...r.kernel.org> Subject: Re: [PATCH v4 06/17] PCI: add SIOV and IMS capability detection On Fri, Nov 13, 2020 at 02:42:02AM +0000, Tian, Kevin wrote: > CPUID#1_ECX is a x86 thing. Do we need to figure out probably_on_ > bare_metal for every architecture altogether, or is it OK to just > handle it for x86 arch at this stage? Based on previous discussions > ims is just one piece of multiple technologies to enable SIOV-like > scalability. Ideally arch-specific enablement beyond ims (e.g. the > IOMMU part) will be required for such scaled usage thus we > may just leave ims disabled for non-x86 and wait until that time to > figure out arch specific probably_on_bare_metal? At the very least you need to ensure that pci_subdevice_msi_create_irq_domain() fails entirely on other architectures until they can sort out these sorts of issues.. Jason
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