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Date:   Tue, 17 Nov 2020 15:04:49 +0100
From:   Arnd Bergmann <arnd@...nel.org>
To:     Gustavo Pimentel <Gustavo.Pimentel@...opsys.com>
Cc:     Joao Pinto <Joao.Pinto@...opsys.com>,
        Derek Kiernan <derek.kiernan@...inx.com>,
        Dragan Cvetic <dragan.cvetic@...inx.com>,
        Arnd Bergmann <arnd@...db.de>,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        Jonathan Corbet <corbet@....net>,
        linux-pci <linux-pci@...r.kernel.org>,
        "open list:DOCUMENTATION" <linux-doc@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        Kishon Vijay Abraham I <kishon@...com>,
        Lorenzo Pieralisi <lorenzo.pieralisi@....com>
Subject: Re: [PATCH v2 0/5] misc: Add Add Synopsys DesignWare xData IP driver

On Fri, Nov 13, 2020 at 11:37 PM Gustavo Pimentel
<Gustavo.Pimentel@...opsys.com> wrote:
>
> This patch series adds a new driver called xData-pcie for the Synopsys
> DesignWare PCIe prototype.
>
> The driver configures and enables the Synopsys DesignWare PCIe traffic
> generator IP inside of prototype Endpoint which will generate upstream
> and downstream PCIe traffic. This allows to quickly test the PCIe link
> throughput speed and check is the prototype solution has some limitation
> or not.

I don't quite understand what this hardware is, based on your description.
Is this a specific piece of hardware that only serves as a traffic generator,
or a particular hardware feature of the DesignWare endpoint, or is it
software running on a SoC in endpoint mode while plugged into a Linux
system running this driver on the host?

Most importantly; Is there any relation between this driver and the driver
we have for the DesignWare PCIe endpoint itself?

My feeling is that this should be located more closely to drivers/pci/,
but that depends on what it actually does.

     Arnd

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