linux-kernel - RE: [PATCH v2 0/5] misc: Add Add Synopsys DesignWare xData IP driver

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Message-ID: <DM5PR12MB18352E62E07B9FBDDB89F1A9DAE20@DM5PR12MB1835.namprd12.prod.outlook.com>
Date:   Tue, 17 Nov 2020 14:53:51 +0000
From:   Gustavo Pimentel <Gustavo.Pimentel@...opsys.com>
To:     Arnd Bergmann <arnd@...nel.org>
CC:     Joao Pinto <Joao.Pinto@...opsys.com>,
        Derek Kiernan <derek.kiernan@...inx.com>,
        Dragan Cvetic <dragan.cvetic@...inx.com>,
        Arnd Bergmann <arnd@...db.de>,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        Jonathan Corbet <corbet@....net>,
        linux-pci <linux-pci@...r.kernel.org>,
        "open list:DOCUMENTATION" <linux-doc@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        Kishon Vijay Abraham I <kishon@...com>,
        Lorenzo Pieralisi <lorenzo.pieralisi@....com>
Subject: RE: [PATCH v2 0/5] misc: Add Add Synopsys DesignWare xData IP driver

On Tue, Nov 17, 2020 at 14:4:49, Arnd Bergmann <arnd@...nel.org> wrote:

> On Fri, Nov 13, 2020 at 11:37 PM Gustavo Pimentel
> <Gustavo.Pimentel@...opsys.com> wrote:
> >
> > This patch series adds a new driver called xData-pcie for the Synopsys
> > DesignWare PCIe prototype.
> >
> > The driver configures and enables the Synopsys DesignWare PCIe traffic
> > generator IP inside of prototype Endpoint which will generate upstream
> > and downstream PCIe traffic. This allows to quickly test the PCIe link
> > throughput speed and check is the prototype solution has some limitation
> > or not.
> 
> I don't quite understand what this hardware is, based on your description.
> Is this a specific piece of hardware that only serves as a traffic generator,
> or a particular hardware feature of the DesignWare endpoint, or is it
> software running on a SoC in endpoint mode while plugged into a Linux
> system running this driver on the host?

Hi Arnd,

Firstly you have to have in mind that we are talking about an HW 
prototype based on FPGA. This PCIe Endpoint HW prototype from Synopsys 
might have multiple HW blocks inside (depends on the HW design), in this 
particular prototype case, it has an HW block is called xData (available 
internally to Synopsys only) which is a PCIe traffic generator, this 
block has no practical usage, unless for HW validation and testing new 
designs that push forward new PCIe speeds.

> 
> Most importantly; Is there any relation between this driver and the driver
> we have for the DesignWare PCIe endpoint itself?

The scopes are different. The DesignWare PCIe endpoint is a framework 
that allows to test some PCIe generic functionalities (not related to 
xData) using pcitest.

> 
> My feeling is that this should be located more closely to drivers/pci/,
> but that depends on what it actually does.

I thought to put on /misc because the purpose is very limited and doesn't 
fit in a normal case.

-Gustavo

> 
>      Arnd