linux-kernel - Re: [PATCH v1] net: mvpp2: divide fifo for dts-active ports only

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Date:   Mon, 23 Nov 2020 15:30:28 +0000
From:   Russell King - ARM Linux admin <linux@...linux.org.uk>
To:     stefanc@...vell.com
Cc:     netdev@...r.kernel.org, thomas.petazzoni@...tlin.com,
        davem@...emloft.net, nadavh@...vell.com, ymarkman@...vell.com,
        linux-kernel@...r.kernel.org, kuba@...nel.org, mw@...ihalf.com,
        andrew@...n.ch
Subject: Re: [PATCH v1] net: mvpp2: divide fifo for dts-active ports only

On Mon, Nov 23, 2020 at 03:10:49PM +0000, Russell King - ARM Linux admin wrote:
> Hi,
> 
> On Mon, Nov 23, 2020 at 04:52:40PM +0200, stefanc@...vell.com wrote:
> > From: Stefan Chulski <stefanc@...vell.com>
> > 
> > Tx/Rx FIFO is a HW resource limited by total size, but shared
> > by all ports of same CP110 and impacting port-performance.
> > Do not divide the FIFO for ports which are not enabled in DTS,
> > so active ports could have more FIFO.
> > 
> > The active port mapping should be done in probe before FIFO-init.
> 
> It would be nice to know what the effect is from this - is it a
> small or large boost in performance?
> 
> What is the effect when the ports on a CP110 are configured for
> 10G, 1G, and 2.5G in that order, as is the case on the Macchiatobin
> board?

(dropped Antoine, his email is bouncing.)

I've rechecked, and on Macchiatobin, it certainly is:
Port 0 = 10G SFP/88x3310
Port 1 = 1G dedicated ethernet
Port 2 = 1G/2.5G SFP slot

and we do run the SFP slot at 2.5G speeds.

-- 
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
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