linux-kernel - Re: [EXT] Re: [PATCH v1] net: mvpp2: divide fifo for dts-active ports only

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Message-ID: <20201123153332.GW1551@shell.armlinux.org.uk>
Date:   Mon, 23 Nov 2020 15:33:32 +0000
From:   Russell King - ARM Linux admin <linux@...linux.org.uk>
To:     Stefan Chulski <stefanc@...vell.com>
Cc:     "netdev@...r.kernel.org" <netdev@...r.kernel.org>,
        "thomas.petazzoni@...tlin.com" <thomas.petazzoni@...tlin.com>,
        "davem@...emloft.net" <davem@...emloft.net>,
        Nadav Haklai <nadavh@...vell.com>,
        Yan Markman <ymarkman@...vell.com>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "kuba@...nel.org" <kuba@...nel.org>,
        "mw@...ihalf.com" <mw@...ihalf.com>,
        "antoine.tenart@...tlin.com" <antoine.tenart@...tlin.com>,
        "andrew@...n.ch" <andrew@...n.ch>
Subject: Re: [EXT] Re: [PATCH v1] net: mvpp2: divide fifo for dts-active
 ports only

On Mon, Nov 23, 2020 at 03:26:11PM +0000, Stefan Chulski wrote:
> > -----Original Message-----
> > From: Russell King - ARM Linux admin <linux@...linux.org.uk>
> > Sent: Monday, November 23, 2020 5:11 PM
> > To: Stefan Chulski <stefanc@...vell.com>
> > Cc: netdev@...r.kernel.org; thomas.petazzoni@...tlin.com;
> > davem@...emloft.net; Nadav Haklai <nadavh@...vell.com>; Yan Markman
> > <ymarkman@...vell.com>; linux-kernel@...r.kernel.org; kuba@...nel.org;
> > mw@...ihalf.com; antoine.tenart@...tlin.com; andrew@...n.ch
> > Subject: [EXT] Re: [PATCH v1] net: mvpp2: divide fifo for dts-active ports only
> > 
> > External Email
> > 
> > ----------------------------------------------------------------------
> > Hi,
> > 
> > On Mon, Nov 23, 2020 at 04:52:40PM +0200, stefanc@...vell.com wrote:
> > > From: Stefan Chulski <stefanc@...vell.com>
> > >
> > > Tx/Rx FIFO is a HW resource limited by total size, but shared by all
> > > ports of same CP110 and impacting port-performance.
> > > Do not divide the FIFO for ports which are not enabled in DTS, so
> > > active ports could have more FIFO.
> > >
> > > The active port mapping should be done in probe before FIFO-init.
> > 
> > It would be nice to know what the effect is from this - is it a small or large
> > boost in performance?
> 
> I didn't saw any significant improvement with LINUX bridge or forwarding, but
> this reduced PPv2 overruns drops, reduced CRC sent errors with DPDK user space application.
> So this improved zero loss throughput. Probably with XDP we would see a similar effect.
> 
> > What is the effect when the ports on a CP110 are configured for 10G, 1G, and
> > 2.5G in that order, as is the case on the Macchiatobin board?
> 
> Macchiatobin has two CP's.  CP1 has 3 ports, so the distribution of FIFO would be the same as before.
> On CP0 which has a single port, all FIFO would be allocated for 10G port.

Your code allocates for CP1:

32K to port 0 (the 10G port on Macchiatobin)
8K to port 1 (the 1G dedicated ethernet port on Macchiatobin)
4K to port 2 (the 1G/2.5G SFP port on Macchiatobin)

I'm questioning that allocation for port 1 and 2.

-- 
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