linux-kernel - Re: [RESEND PATCH 07/19] arm64: dts: allwinner: A100: Add PMU mode

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Message-ID: <803fa6fb-31a2-e90d-a7cc-98f282cec2b1@arm.com>
Date:   Sat, 28 Nov 2020 20:47:43 +0000
From:   André Przywara <andre.przywara@....com>
To:     Frank Lee <frank@...winnertech.com>, tiny.windzz@...il.com
Cc:     devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        Maxime Ripard <mripard@...nel.org>,
        Chen-Yu Tsai <wens@...e.org>, Rob Herring <robh+dt@...nel.org>,
        linux-arm-kernel@...ts.infradead.org,
        Jernej Skrabec <jernej.skrabec@...l.net>
Subject: Re: [RESEND PATCH 07/19] arm64: dts: allwinner: A100: Add PMU mode

On 10/11/2020 06:31, Frank Lee wrote:

Hi,

> From: Yangtao Li <frank@...winnertech.com>
> 
> Add the Performance Monitoring Unit (PMU) device tree node to the A100
> .dtsi, which tells DT users which interrupts are triggered by PMU overflow
> events on each core.

Have you tested that the interrupts actually work? For the A64 there
were wrong in the manual, and we realised only later.
"perf stat" works even without interrupts, but "perf record" requires
interrupts, and will return empty-handed if they don't work.
Can you confirm this?

> 
> Signed-off-by: Yangtao Li <frank@...winnertech.com>

Without being able to test or verify this, the nodes looks correct, so:

Reviewed-by: Andre Przywara <andre.przywara@....com>

Cheers,
Andre

> ---
>  arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi | 15 ++++++++++++---
>  1 file changed, 12 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
> index c34ed8045363..01ff53b5a7a8 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
> @@ -25,21 +25,21 @@ cpu0: cpu@0 {
>  			enable-method = "psci";
>  		};
>  
> -		cpu@1 {
> +		cpu1: cpu@1 {
>  			compatible = "arm,cortex-a53";
>  			device_type = "cpu";
>  			reg = <0x1>;
>  			enable-method = "psci";
>  		};
>  
> -		cpu@2 {
> +		cpu2: cpu@2 {
>  			compatible = "arm,cortex-a53";
>  			device_type = "cpu";
>  			reg = <0x2>;
>  			enable-method = "psci";
>  		};
>  
> -		cpu@3 {
> +		cpu3: cpu@3 {
>  			compatible = "arm,cortex-a53";
>  			device_type = "cpu";
>  			reg = <0x3>;
> @@ -47,6 +47,15 @@ cpu@3 {
>  		};
>  	};
>  
> +	pmu {
> +		compatible = "arm,cortex-a53-pmu";
> +		interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
> +		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
> +	};
> +
>  	psci {
>  		compatible = "arm,psci-1.0";
>  		method = "smc";
>