linux-kernel - Re: [RFC PATCH 1/3] dt-bindings: net: sparx5: Add sparx5-switch bindings

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Message-ID: <20201130140516.GC2073444@lunn.ch>
Date:   Mon, 30 Nov 2020 15:05:16 +0100
From:   Andrew Lunn <andrew@...n.ch>
To:     Steen Hegelund <steen.hegelund@...rochip.com>
Cc:     "David S. Miller" <davem@...emloft.net>,
        Jakub Kicinski <kuba@...nel.org>,
        Rob Herring <robh+dt@...nel.org>,
        Lars Povlsen <lars.povlsen@...rochip.com>,
        Bjarni Jonasson <bjarni.jonasson@...rochip.com>,
        Microchip Linux Driver Support <UNGLinuxDriver@...rochip.com>,
        Alexandre Belloni <alexandre.belloni@...tlin.com>,
        Microsemi List <microsemi@...ts.bootlin.com>,
        netdev@...r.kernel.org, linux-kernel@...r.kernel.org,
        devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org
Subject: Re: [RFC PATCH 1/3] dt-bindings: net: sparx5: Add sparx5-switch
 bindings

On Mon, Nov 30, 2020 at 02:09:34PM +0100, Steen Hegelund wrote:
> On 27.11.2020 18:00, Andrew Lunn wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> > 
> > > +  reg-names:
> > > +    minItems: 153
> > > +    items:
> > > +      - const: dev2g5_0
> > > +      - const: dev5g_0
> > > +      - const: pcs5g_br_0
> > > +      - const: dev2g5_1
> > > +      - const: dev5g_1
> > ...
> > > +      - const: ana_ac
> > > +      - const: vop
> > 
> > > +    switch: switch@...000000 {
> > > +      compatible = "microchip,sparx5-switch";
> > > +      reg = <0x10004000 0x4000>, /* dev2g5_0 */
> > > +        <0x10008000 0x4000>, /* dev5g_0 */
> > > +        <0x1000c000 0x4000>, /* pcs5g_br_0 */
> > > +        <0x10010000 0x4000>, /* dev2g5_1 */
> > > +        <0x10014000 0x4000>, /* dev5g_1 */
> > 
> > ...
> > 
> > > +        <0x11800000 0x100000>, /* ana_l2 */
> > > +        <0x11900000 0x100000>, /* ana_ac */
> > > +        <0x11a00000 0x100000>; /* vop */
> > 
> > This is a pretty unusual binding.
> > 
> > Why is it not
> > 
> > reg = <0x10004000 0x1af8000>
> > 
> > and the driver can then break up the memory into its sub ranges?
> > 
> >    Andrew
> Hi Andrew,
> 
> Since the targets used by the driver is not always in the natural
> address order (e.g. the dev2g5_x targets), I thought it best to let the DT
> take care of this since this cannot be probed.  I am aware that this causes
> extra mappings compared to the one-range strategy, but this layout seems more
> transparent to me, also when mapped over PCIe.

The question is, do you have a device tree usage for this? Are there
devices in the family which have the regions in a different order?

You can easily move this table into the driver, and let the driver
break the region up. That would be normal.

      Andrew