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Date: Wed, 2 Dec 2020 14:38:02 +0000 From: "Zulkifli, Muhammad Husaini" <muhammad.husaini.zulkifli@...el.com> To: Andy Shevchenko <andy.shevchenko@...il.com>, Ulf Hansson <ulf.hansson@...aro.org> CC: "Shevchenko, Andriy" <andriy.shevchenko@...el.com>, Linus Walleij <linus.walleij@...aro.org>, "Hunter, Adrian" <adrian.hunter@...el.com>, Michal Simek <michal.simek@...inx.com>, "linux-mmc@...r.kernel.org" <linux-mmc@...r.kernel.org>, Linux ARM <linux-arm-kernel@...ts.infradead.org>, Linux Kernel Mailing List <linux-kernel@...r.kernel.org>, "Raja Subramanian, Lakshmi Bai" <lakshmi.bai.raja.subramanian@...el.com>, "Wan Mohamad, Wan Ahmad Zainie" <wan.ahmad.zainie.wan.mohamad@...el.com>, Mark Gross <mgross@...ux.intel.com> Subject: RE: [PATCH v6 0/4] mmc: sdhci-of-arasan: Enable UHS-1 support for Keem Bay SOC >-----Original Message----- >From: Andy Shevchenko <andy.shevchenko@...il.com> >Sent: Wednesday, December 2, 2020 10:35 PM >To: Ulf Hansson <ulf.hansson@...aro.org> >Cc: Shevchenko, Andriy <andriy.shevchenko@...el.com>; Linus Walleij ><linus.walleij@...aro.org>; Zulkifli, Muhammad Husaini ><muhammad.husaini.zulkifli@...el.com>; Hunter, Adrian ><adrian.hunter@...el.com>; Michal Simek <michal.simek@...inx.com>; linux- >mmc@...r.kernel.org; Linux ARM <linux-arm-kernel@...ts.infradead.org>; >Linux Kernel Mailing List <linux-kernel@...r.kernel.org>; Raja Subramanian, >Lakshmi Bai <lakshmi.bai.raja.subramanian@...el.com>; Wan Mohamad, >Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@...el.com>; Mark >Gross <mgross@...ux.intel.com> >Subject: Re: [PATCH v6 0/4] mmc: sdhci-of-arasan: Enable UHS-1 support for >Keem Bay SOC > >On Wed, Dec 2, 2020 at 4:10 PM Ulf Hansson <ulf.hansson@...aro.org> >wrote: >> On Wed, 2 Dec 2020 at 14:09, Andy Shevchenko ><andy.shevchenko@...il.com> wrote: >> > On Wed, Dec 2, 2020 at 2:44 PM Ulf Hansson <ulf.hansson@...aro.org> >wrote: > >... > >> > My point is that it may be *not* a pin control at all. >> >> Sorry, but I don't quite follow, what is *not* a pinctrl? >> >> According to the information I have received from the previous >> discussions [1], it's clear to me that the ARM SMC call ends up >> changing settings for the I/O-pads. Or did I get that wrong? > >I'm discussing the possible implication of the solution (faking pin >control) you are proposing. >In this case we know that it's a pin control *under the hood of IPC* >(!) but in another hardware generation it may be, for example,custom voltage >regulator. > >What you are proposing seems to me suboptimal and actually lying about >hardware. Because we do not have direct access to control this pad. >What we have is an IPC to firmware. And it's not our business what is under >the hood. > >It seems it was a mistake to talk about these details in the first place because >it brings more confusion about hardware. So, consider that it's not a pin >control from OS perspective, but a firmware magic. Maybe there is some misunderstanding regarding my statement in previous discussion. I quoted "IO Pad" based on the statement in Databook CFG[1][10:7] for AON register. From the Databook itself with additional confirmation from Keem Bay HW SOC Design Architect, there is no direct control of these AON register bits from GPIO pads. > >-- >With Best Regards, >Andy Shevchenko
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