linux-kernel - Re: [PATCH v8 3/4] phy: Add Sparx5 ethernet serdes PHY driver

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <20201204135532.GK1551@shell.armlinux.org.uk>
Date:   Fri, 4 Dec 2020 13:55:33 +0000
From:   Russell King - ARM Linux admin <linux@...linux.org.uk>
To:     Steen Hegelund <steen.hegelund@...rochip.com>
Cc:     Andrew Lunn <andrew@...n.ch>,
        Kishon Vijay Abraham I <kishon@...com>,
        Vinod Koul <vkoul@...nel.org>,
        linux-arm-kernel@...ts.infradead.org,
        Alexandre Belloni <alexandre.belloni@...tlin.com>,
        Lars Povlsen <lars.povlsen@...rochip.com>,
        Bjarni Jonasson <bjarni.jonasson@...rochip.com>,
        Microchip UNG Driver List <UNGLinuxDriver@...rochip.com>,
        netdev@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v8 3/4] phy: Add Sparx5 ethernet serdes PHY driver

On Fri, Dec 04, 2020 at 02:48:26PM +0100, Steen Hegelund wrote:
> On 03.12.2020 22:52, Andrew Lunn wrote:
> > What i have not yet seen is how this code plugs together with
> > phylink_pcs_ops?
> > 
> > Can this hardware also be used for SATA, USB? As far as i understand,
> > the Marvell Comphy is multi-purpose, it is used for networking, USB,
> > and SATA, etc. Making it a generic PHY then makes sense, because
> > different subsystems need to use it.
> > 
> > But it looks like this is for networking only? So i'm wondering if it
> > belongs in driver/net/pcs and it should be accessed using
> > phylink_pcs_ops?
> > 
> >        Andrew
> 
> This is a PHY that communicates on a SerDes link to an ethernet PHY or a
> SFP. So I took the lead from earlier work: the Microsemi Ocelot SerDes driver,
> and added the Sparx5 SerDes PHY driver here since it is very similar in intent.
> It is not an ethernet PHY as such.

Okay, that is the normal situation in real hardware:

MAC <---> PCS PHY <---> SerDes PHY <---> SerDes lanes

where the PCS PHY handles the protocol level, and the SerDes PHY handles
the clocking and electrical characteristics of the SerDes lanes.

Maybe we should ask for a diagram of the setups when new support is
submitted to make the process of understanding the hardware easier?

-- 
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last!