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Message-ID: <CAFBinCAdQ7PdJ8OpM9iu2fM_7C7KEbWoP9UaFya+uA-ktUs4eg@mail.gmail.com>
Date: Sat, 5 Dec 2020 14:14:51 +0100
From: Martin Blumenstingl <martin.blumenstingl@...glemail.com>
To: Stefan Agner <stefan@...er.ch>
Cc: khilman@...libre.com, robh+dt@...nel.org,
Neil Armstrong <narmstrong@...libre.com>, jbrunet@...libre.com,
christianshewitt@...il.com, jian.hu@...ogic.com,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-amlogic@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 5/5] arm64: dts: meson: g12b: w400: fix PHY deassert
timing requirements
On Tue, Dec 1, 2020 at 2:21 PM Stefan Agner <stefan@...er.ch> wrote:
>
> According to the datasheet (Rev. 1.9) the RTL8211F requires at least
> 72ms "for internal circuits settling time" before accessing the PHY
> egisters. On similar boards with the same PHY this fixes an issue where
> Ethernet link would not come up when using ip link set down/up.
>
> Fixes: 2cd2310fca4c ("arm64: dts: meson-g12b-ugoos-am6: add initial device-tree")
> Signed-off-by: Stefan Agner <stefan@...er.ch>
with the "registers" typo above fixed:
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@...glemail.com>
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