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Message-ID: <CAL_JsqK3bbp-50fu498nN+p1rmRBSyX4ctbz9tgfPFA8GqPiCg@mail.gmail.com>
Date:   Mon, 7 Dec 2020 08:18:26 -0600
From:   Rob Herring <robh@...nel.org>
To:     Vidya Sagar <vidyas@...dia.com>
Cc:     Jingoo Han <jingoohan1@...il.com>,
        Gustavo Pimentel <gustavo.pimentel@...opsys.com>,
        Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
        Bjorn Helgaas <bhelgaas@...gle.com>,
        Andrew Murray <amurray@...goodpenguin.co.uk>,
        Thierry Reding <treding@...dia.com>,
        Jon Hunter <jonathanh@...dia.com>,
        PCI <linux-pci@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        kthota@...dia.com, Manikanta Maddireddy <mmaddireddy@...dia.com>,
        sagar.tv@...il.com
Subject: Re: [PATCH] PCI: dwc: Add support to configure for ECRC

On Mon, Nov 9, 2020 at 1:26 PM Vidya Sagar <vidyas@...dia.com> wrote:
>
> DesignWare core has a TLP digest (TD) override bit in one of the control
> registers of ATU. This bit also needs to be programmed for proper ECRC
> functionality. This is currently identified as an issue with DesignWare
> IP version 4.90a.
>
> Signed-off-by: Vidya Sagar <vidyas@...dia.com>
> ---
>  drivers/pci/controller/dwc/pcie-designware.c | 50 ++++++++++++++++++--
>  drivers/pci/controller/dwc/pcie-designware.h |  1 +
>  2 files changed, 47 insertions(+), 4 deletions(-)

Reviewed-by: Rob Herring <robh@...nel.org>

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