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Message-Id: <1607413467-17698-3-git-send-email-zhangqing@loongson.cn>
Date:   Tue,  8 Dec 2020 15:44:26 +0800
From:   Qing Zhang <zhangqing@...ngson.cn>
To:     Mark Brown <broonie@...nel.org>, Rob Herring <robh+dt@...nel.org>,
        Thomas Bogendoerfer <tsbogend@...ha.franken.de>
Cc:     linux-spi@...r.kernel.org, Huacai Chen <chenhc@...ote.com>,
        Jiaxun Yang <jiaxun.yang@...goat.com>,
        devicetree@...r.kernel.org, linux-mips@...r.kernel.org,
        linux-kernel@...r.kernel.org, gaojuxin@...ngson.cn,
        yangtiezhu@...ngson.cn
Subject: [PATCH v2 3/4] MIPS: Loongson64: DTS: Add SPI support to LS7A

add spi and amd node support.

Signed-off-by: Qing Zhang <zhangqing@...ngson.cn>
---

v2:
- Add spi about pci device DT
---
 arch/mips/boot/dts/loongson/ls7a-pch.dtsi | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/arch/mips/boot/dts/loongson/ls7a-pch.dtsi b/arch/mips/boot/dts/loongson/ls7a-pch.dtsi
index f99a7a1..ab8836b 100644
--- a/arch/mips/boot/dts/loongson/ls7a-pch.dtsi
+++ b/arch/mips/boot/dts/loongson/ls7a-pch.dtsi
@@ -405,6 +405,26 @@
 				interrupt-map-mask = <0 0 0 0>;
 				interrupt-map = <0 0 0 0 &pic 39 IRQ_TYPE_LEVEL_HIGH>;
 			};
+
+			spi@16,0 {
+				compatible = "pci0014,7a0b.0",
+						"pci0014,7a0b",
+						"pciclass088000",
+						"pciclass0880";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				reg = <0xb000 0x0 0x0 0x0 0x0>;
+				num-chipselects = <0>;
+				spiflash: s25fl016k@0 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				compatible ="spansion,s25fl016k","jedec,spi-nor";
+				spi-max-frequency=<50000000>;
+				reg=<0>;
+				};
+			};
 		};
 
 		isa {
-- 
2.1.0

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