linux-kernel - Re: [PATCH v3 1/2] dt-bindings: riscv: Update l2 cache DT documentation to add support for SiFive FU740

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Date:   Thu, 10 Dec 2020 21:46:44 -0600
From:   Rob Herring <robh@...nel.org>
To:     Yash Shah <yash.shah@...ive.com>
Cc:     anup@...infault.org, bp@...e.de, paul.walmsley@...ive.com,
        sagar.kadam@...ive.com, sachin.ghadi@...ive.com,
        devicetree@...r.kernel.org, palmer@...belt.com,
        linux-kernel@...r.kernel.org, linux-riscv@...ts.infradead.org,
        robh+dt@...nel.org, aou@...s.berkeley.edu,
        Jonathan.Cameron@...wei.com, sam@...nborg.org, wsa@...nel.org
Subject: Re: [PATCH v3 1/2] dt-bindings: riscv: Update l2 cache DT
 documentation to add support for SiFive FU740

On Thu, 10 Dec 2020 15:58:02 +0530, Yash Shah wrote:
> The L2 cache controller in SiFive FU740 has 4 ECC interrupt sources as
> compared to 3 in FU540. Update the DT documentation accordingly with
> "compatible" and "interrupt" property changes.
> 
> Signed-off-by: Yash Shah <yash.shah@...ive.com>
> ---
>  .../devicetree/bindings/riscv/sifive-l2-cache.yaml | 34 +++++++++++++++++++---
>  1 file changed, 30 insertions(+), 4 deletions(-)
> 

Reviewed-by: Rob Herring <robh@...nel.org>