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Message-ID: <mhng-18249e76-3632-4347-b9f1-73e1cc39683a@palmerdabbelt-glaptop>
Date: Thu, 07 Jan 2021 17:36:18 -0800 (PST)
From: Palmer Dabbelt <palmer@...belt.com>
To: yash.shah@...ive.com
CC: linux-kernel@...r.kernel.org, linux-riscv@...ts.infradead.org,
devicetree@...r.kernel.org, bp@...e.de, anup@...infault.org,
Jonathan.Cameron@...wei.com, wsa@...nel.org, sam@...nborg.org,
aou@...s.berkeley.edu, Paul Walmsley <paul.walmsley@...ive.com>,
robh+dt@...nel.org, sagar.kadam@...ive.com,
sachin.ghadi@...ive.com, yash.shah@...ive.com
Subject: Re: [PATCH v3 0/2] riscv: sifive_l2_cache: Add support for SiFive FU740 SoC
On Thu, 10 Dec 2020 02:28:01 PST (-0800), yash.shah@...ive.com wrote:
> Add support for additional interrupt present in SiFive FU740 chip.
>
> Changes:
> v3:
> - Rename the subject line of dt-binding patch
> - Add the additional interrupt "DirFail" as the last entry so as to keep
> the order of all previous index same.
>
> v2:
> - Changes as per Rob Herring's request on v1
>
> Yash Shah (2):
> dt-bindings: riscv: Update l2 cache DT documentation to add support
> for SiFive FU740
> RISC-V: sifive_l2_cache: Update L2 cache driver to support SiFive
> FU740
>
> .../devicetree/bindings/riscv/sifive-l2-cache.yaml | 34 +++++++++++++++++++---
> drivers/soc/sifive/sifive_l2_cache.c | 27 +++++++++++++++--
> 2 files changed, 54 insertions(+), 7 deletions(-)
Thanks, these are on for-next.
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