linux-kernel - Re: [PATCH] MIPS: Ingenic: Disable HPTLB for D0 XBurst CPUs too

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Date:   Mon, 14 Dec 2020 23:54:58 +0800
From:   Zhou Yanjie <zhouyanjie@...yeetech.com>
To:     Paul Cercueil <paul@...pouillou.net>
Cc:     Thomas Bogendoerfer <tsbogend@...ha.franken.de>,
        Zhou Yanjie <zhouyanjie@...o.com>, od@...c.me,
        linux-mips@...r.kernel.org, linux-kernel@...r.kernel.org,
        stable@...r.kernel.org
Subject: Re: [PATCH] MIPS: Ingenic: Disable HPTLB for D0 XBurst CPUs too

Hi Paul,

On 2020/12/14 上午3:57, Paul Cercueil wrote:
> Hi Zhou,
>
> Le lun. 14 déc. 2020 à 3:12, Zhou Yanjie <zhouyanjie@...yeetech.com> a 
> écrit :
>> Hi Paul,
>>
>> On 2020/12/12 上午8:03, Paul Cercueil wrote:
>>> The JZ4760 has the HPTLB as well, but has a XBurst CPU with a D0 CPUID.
>>>
>>> Disable the HPTLB for all XBurst CPUs with a D0 CPUID. In the case 
>>> where
>>> there is no HPTLB (e.g. for older SoCs), this won't have any side
>>> effect.
>>>
>>> Fixes: b02efeb05699 ("MIPS: Ingenic: Disable abandoned HPTLB 
>>> function.")
>>> Cc: <stable@...r.kernel.org> # 5.4
>>> Signed-off-by: Paul Cercueil <paul@...pouillou.net>
>>> ---
>>>   arch/mips/kernel/cpu-probe.c | 15 ++++++++-------
>>>   1 file changed, 8 insertions(+), 7 deletions(-)
>>>
>>> diff --git a/arch/mips/kernel/cpu-probe.c 
>>> b/arch/mips/kernel/cpu-probe.c
>>> index e6853697a056..31cb9199197c 100644
>>> --- a/arch/mips/kernel/cpu-probe.c
>>> +++ b/arch/mips/kernel/cpu-probe.c
>>> @@ -1830,16 +1830,17 @@ static inline void cpu_probe_ingenic(struct 
>>> cpuinfo_mips *c, unsigned int cpu)
>>>            */
>>>           case PRID_COMP_INGENIC_D0:
>>>               c->isa_level &= ~MIPS_CPU_ISA_M32R2;
>>> -            break;
>>> +            fallthrough;
>>>             /*
>>>            * The config0 register in the XBurst CPUs with a 
>>> processor ID of
>>> -         * PRID_COMP_INGENIC_D1 has an abandoned huge page tlb 
>>> mode, this
>>> -         * mode is not compatible with the MIPS standard, it will 
>>> cause
>>> -         * tlbmiss and into an infinite loop (line 21 in the 
>>> tlb-funcs.S)
>>> -         * when starting the init process. After chip reset, the 
>>> default
>>> -         * is HPTLB mode, Write 0xa9000000 to cp0 register 5 sel 4 to
>>
>>
>> I just noticed that I mistakenly wrote a capital 'W' in the original 
>> version.
>>
>> with that fixed:
>>
>> Reviewed-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@...yeetech.com>
>
> Sure, thanks.
>
> If both D0 and D1 CPUs need the fix then I probably should move it 
> outside the switch, that would make the code a bit cleaner. I'll V2.
>

This is a good idea, but it should be noted that it still needs to be 
placed in XBURST_REV1, because XBURST_REV2 processors (such as X1830) 
also use the ID of D0, but they do not have the problem of HPTLB.


>> BTW: Are you planning to add support for JZ4760 recently? I am 
>> currently writing the CGU driver for JZ4775 and X2000. If you plan to 
>> add support for JZ4760, I can also write the CGU driver for JZ4760 by 
>> the way.
>
> Yes, we're working on it, all the core drivers are working (CGU, 
> pinctrl, timers, display, USB), it boots to userspace and allows to 
> telnet. The actual diff is very small, most of the changes were the 
> addition of the ingenic,jz4760-* compatible strings.
>

Good to hear that.

Thanks and best regards!


> Cheers,
> -Paul
>
>>> -         * switch back to VTLB mode to prevent getting stuck.
>>> +         * PRID_COMP_INGENIC_D0 or PRID_COMP_INGENIC_D1 has an 
>>> abandoned
>>> +         * huge page tlb mode, this mode is not compatible with the 
>>> MIPS
>>> +         * standard, it will cause tlbmiss and into an infinite loop
>>> +         * (line 21 in the tlb-funcs.S) when starting the init 
>>> process.
>>> +         * After chip reset, the default is HPTLB mode, Write 
>>> 0xa9000000
>>> +         * to cp0 register 5 sel 4 to switch back to VTLB mode to 
>>> prevent
>>> +         * getting stuck.
>>>            */
>>>           case PRID_COMP_INGENIC_D1:
>>>               write_c0_page_ctrl(XBURST_PAGECTRL_HPTLB_DIS);
>