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Date: Mon, 14 Dec 2020 16:56:59 +0100 From: Ulf Hansson <ulf.hansson@...aro.org> To: Andrew Jeffery <andrew@...id.au> Cc: "linux-mmc@...r.kernel.org" <linux-mmc@...r.kernel.org>, Rob Herring <robh+dt@...nel.org>, Joel Stanley <joel@....id.au>, Adrian Hunter <adrian.hunter@...el.com>, Linux Kernel Mailing List <linux-kernel@...r.kernel.org>, DTML <devicetree@...r.kernel.org>, Linux ARM <linux-arm-kernel@...ts.infradead.org>, linux-aspeed <linux-aspeed@...ts.ozlabs.org>, ryan_chen@...eedtech.com Subject: Re: [PATCH v5 0/6] mmc: sdhci-of-aspeed: Expose phase delay tuning On Tue, 8 Dec 2020 at 02:26, Andrew Jeffery <andrew@...id.au> wrote: > > Hello, > > This series implements support for the MMC core clk-phase-* devicetree bindings > in the Aspeed SD/eMMC driver. The relevant register was exposed on the AST2600 > and is present for both the SD/MMC controller and the dedicated eMMC > controller. > > v5 fixes some build issues identified by the kernel test robot. > > v4 can be found here: > > https://lore.kernel.org/linux-mmc/20201207142556.2045481-1-andrew@aj.id.au/ > > The series has had light testing on an AST2600-based platform which requires > 180deg of input and output clock phase correction at HS200, as well as some > synthetic testing under qemu and KUnit. > > Please review! FYI, other than the comment I had on patch1, I think the series looks good to me. [...] Kind regards Uffe
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