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Date: Wed, 16 Dec 2020 05:24:41 +0000 From: Yash Shah <yash.shah@...nfive.com> To: Bin Meng <bmeng.cn@...il.com> CC: "linux-spi@...r.kernel.org" <linux-spi@...r.kernel.org>, "linux-serial@...r.kernel.org" <linux-serial@...r.kernel.org>, "linux-pwm@...r.kernel.org" <linux-pwm@...r.kernel.org>, "linux-i2c@...r.kernel.org" <linux-i2c@...r.kernel.org>, linux-kernel <linux-kernel@...r.kernel.org>, linux-riscv <linux-riscv@...ts.infradead.org>, devicetree <devicetree@...r.kernel.org>, "open list:GPIO SUBSYSTEM" <linux-gpio@...r.kernel.org>, "broonie@...nel.org" <broonie@...nel.org>, Greg Kroah-Hartman <gregkh@...uxfoundation.org>, Albert Ou <aou@...s.berkeley.edu>, "lee.jones@...aro.org" <lee.jones@...aro.org>, "u.kleine-koenig@...gutronix.de" <u.kleine-koenig@...gutronix.de>, Thierry Reding <thierry.reding@...il.com>, "andrew@...n.ch" <andrew@...n.ch>, Peter Korsgaard <peter@...sgaard.com>, "Paul Walmsley ( Sifive)" <paul.walmsley@...ive.com>, Palmer Dabbelt <palmer@...belt.com>, Rob Herring <robh+dt@...nel.org>, Bartosz Golaszewski <bgolaszewski@...libre.com>, Linus Walleij <linus.walleij@...aro.org> Subject: RE: [PATCH v2 7/9] riscv: dts: add initial support for the SiFive FU740-C000 SoC > -----Original Message----- > From: Bin Meng <bmeng.cn@...il.com> > Sent: 10 December 2020 19:05 > To: Yash Shah <yash.shah@...nfive.com> > Cc: linux-spi@...r.kernel.org; linux-serial@...r.kernel.org; linux- > pwm@...r.kernel.org; linux-i2c@...r.kernel.org; linux-kernel <linux- > kernel@...r.kernel.org>; linux-riscv <linux-riscv@...ts.infradead.org>; > devicetree <devicetree@...r.kernel.org>; open list:GPIO SUBSYSTEM <linux- > gpio@...r.kernel.org>; broonie@...nel.org; Greg Kroah-Hartman > <gregkh@...uxfoundation.org>; Albert Ou <aou@...s.berkeley.edu>; > lee.jones@...aro.org; u.kleine-koenig@...gutronix.de; Thierry Reding > <thierry.reding@...il.com>; andrew@...n.ch; Peter Korsgaard > <peter@...sgaard.com>; Paul Walmsley ( Sifive) > <paul.walmsley@...ive.com>; Palmer Dabbelt <palmer@...belt.com>; Rob > Herring <robh+dt@...nel.org>; Bartosz Golaszewski > <bgolaszewski@...libre.com>; Linus Walleij <linus.walleij@...aro.org> > Subject: Re: [PATCH v2 7/9] riscv: dts: add initial support for the SiFive FU740- > C000 SoC > > [External Email] Do not click links or attachments unless you recognize the > sender and know the content is safe > > On Tue, Dec 8, 2020 at 3:06 PM Yash Shah <yash.shah@...ive.com> wrote: > > > > Add initial support for the SiFive FU540-C000 SoC. FU740-C000 is built > > FU740-C000 Soc > > > around the SiFIve U7 Core Complex and a TileLink interconnect. > > > > This file is expected to grow as more device drivers are added to the > > kernel. > > > > Signed-off-by: Yash Shah <yash.shah@...ive.com> > > --- > > arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 293 > > +++++++++++++++++++++++++++++ > > 1 file changed, 293 insertions(+) > > create mode 100644 arch/riscv/boot/dts/sifive/fu740-c000.dtsi > > > > diff --git a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi > > b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi > > new file mode 100644 > > index 0000000..eeb4f8c3 > > --- /dev/null > > +++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi > > @@ -0,0 +1,293 @@ ... > > + plic0: interrupt-controller@...0000 { > > + #interrupt-cells = <1>; > > + #address-cells = <0>; > > + compatible = "sifive,fu540-c000-plic", > > + "sifive,plic-1.0.0"; > > I don't see bindings updated for FU740 PLIC, like "sifive,fu740-c000-plic"? That's because it is not required. There won't be any difference in driver code for FU740 plic. ... > > + eth0: ethernet@...90000 { > > + compatible = "sifive,fu540-c000-gem"; > > "sifive,fu740-c000-gem"? > Same reason as above. Thanks for your review. - Yash > > + interrupt-parent = <&plic0>; > > + interrupts = <55>; > > + reg = <0x0 0x10090000 0x0 0x2000>, > > + <0x0 0x100a0000 0x0 0x1000>; > > + local-mac-address = [00 00 00 00 00 00]; > > + clock-names = "pclk", "hclk"; > > + clocks = <&prci PRCI_CLK_GEMGXLPLL>, > > + <&prci PRCI_CLK_GEMGXLPLL>; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + status = "disabled"; > > + }; > > + pwm0: pwm@...20000 { > > + compatible = "sifive,fu740-c000-pwm", "sifive,pwm0"; > > + reg = <0x0 0x10020000 0x0 0x1000>; > > + interrupt-parent = <&plic0>; > > + interrupts = <44>, <45>, <46>, <47>; > > + clocks = <&prci PRCI_CLK_PCLK>; > > + #pwm-cells = <3>; > > + status = "disabled"; > > + }; > > + pwm1: pwm@...21000 { > > + compatible = "sifive,fu740-c000-pwm", "sifive,pwm0"; > > + reg = <0x0 0x10021000 0x0 0x1000>; > > + interrupt-parent = <&plic0>; > > + interrupts = <48>, <49>, <50>, <51>; > > + clocks = <&prci PRCI_CLK_PCLK>; > > + #pwm-cells = <3>; > > + status = "disabled"; > > + }; > > + ccache: cache-controller@...0000 { > > + compatible = "sifive,fu740-c000-ccache", "cache"; > > + cache-block-size = <64>; > > + cache-level = <2>; > > + cache-sets = <2048>; > > + cache-size = <2097152>; > > + cache-unified; > > + interrupt-parent = <&plic0>; > > + interrupts = <19 20 21 22>; > > + reg = <0x0 0x2010000 0x0 0x1000>; > > + }; > > + gpio: gpio@...60000 { > > + compatible = "sifive,fu740-c000-gpio", "sifive,gpio0"; > > + interrupt-parent = <&plic0>; > > + interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>, > > + <30>, <31>, <32>, <33>, <34>, <35>, <36>, > > + <37>, <38>; > > + reg = <0x0 0x10060000 0x0 0x1000>; > > + gpio-controller; > > + #gpio-cells = <2>; > > + interrupt-controller; > > + #interrupt-cells = <2>; > > + clocks = <&prci PRCI_CLK_PCLK>; > > + status = "disabled"; > > + }; > > + }; > > +}; > > Regards, > Bin
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