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Message-ID: <160840763464.1580929.12880803082811509442@swboyd.mtv.corp.google.com>
Date:   Sat, 19 Dec 2020 11:53:54 -0800
From:   Stephen Boyd <sboyd@...nel.org>
To:     Claudiu Beznea <claudiu.beznea@...rochip.com>,
        alexandre.belloni@...tlin.com, ludovic.desroches@...rochip.com,
        mturquette@...libre.com, nicolas.ferre@...rochip.com,
        robh+dt@...nel.org
Cc:     linux-clk@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
        Claudiu Beznea <claudiu.beznea@...rochip.com>
Subject: Re: [PATCH v6 06/11] clk: at91: clk-sam9x60-pll: allow runtime changes for pll

Quoting Claudiu Beznea (2020-11-19 07:43:12)
> Allow runtime frequency changes for PLLs registered with proper flags.
> This is necessary for CPU PLL on SAMA7G5 which is used by DVFS.
> 
> Signed-off-by: Claudiu Beznea <claudiu.beznea@...rochip.com>
> ---

Applied to clk-next

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