[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <160842072616.1580929.6874356393849040448@swboyd.mtv.corp.google.com>
Date: Sat, 19 Dec 2020 15:32:06 -0800
From: Stephen Boyd <sboyd@...nel.org>
To: Claudiu Beznea <claudiu.beznea@...rochip.com>,
alexandre.belloni@...tlin.com, ludovic.desroches@...rochip.com,
mturquette@...libre.com, nicolas.ferre@...rochip.com,
robh+dt@...nel.org
Cc: linux-clk@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
Claudiu Beznea <claudiu.beznea@...rochip.com>
Subject: Re: [PATCH v6 08/11] clk: at91: sama7g5: decrease lower limit for MCK0 rate
Quoting Claudiu Beznea (2020-11-19 07:43:14)
> On SAMA7G5 CPU clock is changed at run-time by DVFS. Since MCK0 and
> CPU clock shares the same parent clock (CPUPLL clock) the MCK0 is
> also changed by DVFS to avoid over/under clocking of MCK0 consumers.
> The lower limit is changed to be able to set MCK0 accordingly by
> DVFS.
>
> Signed-off-by: Claudiu Beznea <claudiu.beznea@...rochip.com>
> ---
Applied to clk-next
Powered by blists - more mailing lists