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Message-ID: <160842073181.1580929.17659902836214235882@swboyd.mtv.corp.google.com>
Date:   Sat, 19 Dec 2020 15:32:11 -0800
From:   Stephen Boyd <sboyd@...nel.org>
To:     Claudiu Beznea <claudiu.beznea@...rochip.com>,
        alexandre.belloni@...tlin.com, ludovic.desroches@...rochip.com,
        mturquette@...libre.com, nicolas.ferre@...rochip.com,
        robh+dt@...nel.org
Cc:     linux-clk@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
        Claudiu Beznea <claudiu.beznea@...rochip.com>
Subject: Re: [PATCH v6 09/11] clk: at91: sama7g5: do not allow cpu pll to go higher than 1GHz

Quoting Claudiu Beznea (2020-11-19 07:43:15)
> Since CPU PLL feeds both CPU clock and MCK0, MCK0 cannot go higher
> than 200MHz and MCK0 maximum prescaller is 5 limit the CPU PLL at
> 1GHz to avoid MCK0 overclocking while CPU PLL is changed by DVFS.
> 
> Signed-off-by: Claudiu Beznea <claudiu.beznea@...rochip.com>
> ---

Applied to clk-next

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