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Message-ID: <160842074325.1580929.10681302638864273463@swboyd.mtv.corp.google.com>
Date: Sat, 19 Dec 2020 15:32:23 -0800
From: Stephen Boyd <sboyd@...nel.org>
To: Claudiu Beznea <claudiu.beznea@...rochip.com>,
alexandre.belloni@...tlin.com, ludovic.desroches@...rochip.com,
mturquette@...libre.com, nicolas.ferre@...rochip.com,
robh+dt@...nel.org
Cc: linux-clk@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
Claudiu Beznea <claudiu.beznea@...rochip.com>
Subject: Re: [PATCH v6 11/11] clk: at91: sama7g5: register cpu clock
Quoting Claudiu Beznea (2020-11-19 07:43:17)
> Register CPU clock as being the master clock prescaler. This would
> be used by DVFS. The block schema of SAMA7G5's PMC contains also a divider
> between master clock prescaler and CPU (PMC_CPU_RATIO.RATIO) but the
> frequencies supported by SAMA7G5 could be directly received from
> CPUPLL + master clock prescaler and the extra divider would do no work in
> case it would be enabled.
>
> Signed-off-by: Claudiu Beznea <claudiu.beznea@...rochip.com>
> ---
Applied to clk-next
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