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Message-ID: <CAOnJCUJ5UK3Do=uC0R2DVMNt6HmoJHKB1XXr8MkoeBYNzQHZrw@mail.gmail.com>
Date: Tue, 22 Dec 2020 12:14:27 -0800
From: Atish Patra <atishp@...shpatra.org>
To: Daire McNamara <daire.mcnamara@...rochip.com>
Cc: Atish Patra <Atish.Patra@....com>,
devicetree <devicetree@...r.kernel.org>,
Conor.Dooley@...rochip.com, Anup Patel <Anup.Patel@....com>,
Cyril.Jean@...rochip.com, Bin Meng <bin.meng@...driver.com>,
"linux-kernel@...r.kernel.org List" <linux-kernel@...r.kernel.org>,
Rob Herring <robh+dt@...nel.org>, Ivan.Griffin@...rochip.com,
Albert Ou <aou@...s.berkeley.edu>,
Alistair Francis <Alistair.Francis@....com>,
Paul Walmsley <paul.walmsley@...ive.com>,
linux-riscv <linux-riscv@...ts.infradead.org>,
Palmer Dabbelt <palmer@...belt.com>
Subject: Re: [PATCH v3 0/5] Add Microchip PolarFire Soc Support
On Mon, Dec 21, 2020 at 7:19 PM Palmer Dabbelt <palmer@...belt.com> wrote:
>
> On Fri, 04 Dec 2020 00:58:30 PST (-0800), Atish Patra wrote:
> > This series adds minimal support for Microchip Polar Fire Soc Icicle kit.
> > It is rebased on v5.10-rc6 and depends on clock support.
> > Only MMC and ethernet drivers are enabled via this series.
> > The idea here is to add the foundational patches so that other drivers
> > can be added to on top of this. The device tree may change based on
> > feedback on bindings of individual driver support patches.
> >
> > This series has been tested on Qemu and Polar Fire Soc Icicle kit.
> > The following qemu series is necessary to test it on Qemu.
> >
> > The series can also be found at.
> > https://github.com/atishp04/linux/tree/polarfire_support_upstream_v3
> >
> > I noticed the latest version of mmc driver[2] hangs on the board with
> > the latest clock driver. That's why, I have tested with the old clock
> > driver available in the above github repo.
>
> IIRC the previous version was an RFC, but this is a PATCH. I'd be generally
> happy to take it on for-next, but I don't want to merge something that doesn't
> boot and that I don't have any way to fix (I don't have one of the boards yet).
>
Fair enough. We can wait for clock patches to be merged before merging
this series.
> > [1] https://lists.nongnu.org/archive/html/qemu-devel/2020-10/msg08582.html
> > [2] https://www.spinics.net/lists/devicetree/msg383626.html
> >
> > Changes from v2->v3:
> > 1. Fixed a typo in dt binding.
> > 2. Included MAINTAINERS entry for PolarFire SoC.
> > 3. Improved the dts file by using lowercase clock names and keeping phy
> > details in board specific dts file.
> >
> > Changes from v1->v2:
> > 1. Modified the DT to match the device tree in U-Boot.
> > 2. Added both eMMC & SDcard entries in DT. However, SD card is only enabled
> > as it allows larger storage option for linux distros.
> >
> > Atish Patra (4):
> > RISC-V: Add Microchip PolarFire SoC kconfig option
> > dt-bindings: riscv: microchip: Add YAML documentation for the
> > PolarFire SoC
> > RISC-V: Initial DTS for Microchip ICICLE board
> > RISC-V: Enable Microchip PolarFire ICICLE SoC
> >
> > Conor Dooley (1):
> > MAINTAINERS: add microchip polarfire soc support
> >
> > .../devicetree/bindings/riscv/microchip.yaml | 28 ++
> > MAINTAINERS | 8 +
> > arch/riscv/Kconfig.socs | 7 +
> > arch/riscv/boot/dts/Makefile | 1 +
> > arch/riscv/boot/dts/microchip/Makefile | 2 +
> > .../microchip/microchip-mpfs-icicle-kit.dts | 72 ++++
> > .../boot/dts/microchip/microchip-mpfs.dtsi | 331 ++++++++++++++++++
> > arch/riscv/configs/defconfig | 4 +
> > 8 files changed, 453 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/riscv/microchip.yaml
> > create mode 100644 arch/riscv/boot/dts/microchip/Makefile
> > create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
> > create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
>
> _______________________________________________
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@Daire McNamara Do you have a v2 of the clock patch series that works
with the latest upstream.
--
Regards,
Atish
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