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Date:   Wed, 23 Dec 2020 22:05:21 +0100
From:   Andrew Lunn <>
To:     Alexandre Belloni <>
Cc:     Steen Hegelund <>,
        "David S. Miller" <>,
        Jakub Kicinski <>,
        Russell King <>,
        Lars Povlsen <>,
        Bjarni Jonasson <>,
        Microchip Linux Driver Support <>,
        Madalin Bucur <>,
        Nicolas Ferre <>,
        Mark Einon <>,
        Masahiro Yamada <>,
        Arnd Bergmann <>,,,
Subject: Re: [RFC PATCH v2 3/8] net: sparx5: add hostmode with phylink support

On Wed, Dec 23, 2020 at 09:58:52PM +0100, Alexandre Belloni wrote:
> On 22/12/2020 15:41:41+0100, Andrew Lunn wrote:
> > > Yes the register based injection/extration is not going to be fast, but
> > > the FDMA and its driver is being sent later as separate series to keep
> > > the size of this review down.
> > 
> > FDMA?
> > 
> > I need a bit more background here, just to make use this should be a
> > pure switchdev driver and not a DSA driver.
> > 
> I don't think this should be a DSA driver. As for Ocelot, the CPU
> port is not a MAC and in that use case, this would be like a top of the
> rack switch with traffic going to the CPU port being mostly used for
> managmement (dhcp, stp, etc...) as opposed to being used to forward
> traffic to another interface, like WAN or wifi.
> However, I would think there will be cases where the internal CPU is not
> use and instead use ths switch in a DSA setting, very much like what is
> done for Felix with regards to Ocelot.

>From what i have heard so far, it does seem like a pure switchdev
driver is correct. So long as FDMA is not a standalone Ethernet
driver, but just a DMA engine incorporated into this driver, the
architecture looks correct.

I was asking because from the information that was available, it was
impossible to say what the correct architecture should be.


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