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Message-ID: <20201224111627.32590-12-kishon@ti.com>
Date: Thu, 24 Dec 2020 16:46:23 +0530
From: Kishon Vijay Abraham I <kishon@...com>
To: Kishon Vijay Abraham I <kishon@...com>,
Vinod Koul <vkoul@...nel.org>,
Rob Herring <robh+dt@...nel.org>, Nishanth Menon <nm@...com>,
Philipp Zabel <p.zabel@...gutronix.de>
CC: <linux-kernel@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>
Subject: [PATCH v3 11/15] phy: cadence: sierra: Enable pll_cmnlc and pll_cmnlc1 clocks
Get pll_cmnlc and pll_cmnlc1 optional clocks and enable them.
This will enable REFRCV/1 in case the pll_cmnlc/1 takes input
from REFRCV/1 respectively.
Signed-off-by: Kishon Vijay Abraham I <kishon@...com>
---
drivers/phy/cadence/phy-cadence-sierra.c | 57 +++++++++++++++++++++++-
1 file changed, 55 insertions(+), 2 deletions(-)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c
index 2a509be80c80..ad0ea74515d6 100644
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -267,6 +267,8 @@ struct cdns_sierra_phy {
struct clk *clk;
struct clk *cmn_refclk_dig_div;
struct clk *cmn_refclk1_dig_div;
+ struct clk *pll_cmnlc;
+ struct clk *pll_cmnlc1;
int nsubnodes;
u32 num_lanes;
bool autoconf;
@@ -874,9 +876,59 @@ static int cdns_sierra_phy_get_clocks(struct cdns_sierra_phy *sp,
}
sp->cmn_refclk1_dig_div = clk;
+ clk = devm_clk_get_optional(dev, "pll_cmnlc");
+ if (IS_ERR(clk)) {
+ dev_err(dev, "pll_cmnlc clock not found\n");
+ ret = PTR_ERR(clk);
+ return ret;
+ }
+ sp->pll_cmnlc = clk;
+
+ clk = devm_clk_get_optional(dev, "pll_cmnlc1");
+ if (IS_ERR(clk)) {
+ dev_err(dev, "pll_cmnlc1 clock not found\n");
+ ret = PTR_ERR(clk);
+ return ret;
+ }
+ sp->pll_cmnlc1 = clk;
+
return 0;
}
+static int cdns_sierra_phy_enable_clocks(struct cdns_sierra_phy *sp)
+{
+ int ret;
+
+ ret = clk_prepare_enable(sp->clk);
+ if (ret)
+ return ret;
+
+ ret = clk_prepare_enable(sp->pll_cmnlc);
+ if (ret)
+ goto err_pll_cmnlc;
+
+ ret = clk_prepare_enable(sp->pll_cmnlc1);
+ if (ret)
+ goto err_pll_cmnlc1;
+
+ return 0;
+
+err_pll_cmnlc:
+ clk_disable_unprepare(sp->clk);
+
+err_pll_cmnlc1:
+ clk_disable_unprepare(sp->pll_cmnlc);
+
+ return 0;
+}
+
+static void cdns_sierra_phy_disable_clocks(struct cdns_sierra_phy *sp)
+{
+ clk_disable_unprepare(sp->pll_cmnlc1);
+ clk_disable_unprepare(sp->pll_cmnlc);
+ clk_disable_unprepare(sp->clk);
+}
+
static int cdns_sierra_phy_get_resets(struct cdns_sierra_phy *sp,
struct device *dev)
{
@@ -961,7 +1013,7 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev)
if (ret)
goto unregister_pll_mux;
- ret = clk_prepare_enable(sp->clk);
+ ret = cdns_sierra_phy_enable_clocks(sp);
if (ret)
goto unregister_pll_mux;
@@ -1038,7 +1090,7 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev)
reset_control_put(sp->phys[i].lnk_rst);
of_node_put(child);
clk_disable:
- clk_disable_unprepare(sp->clk);
+ cdns_sierra_phy_disable_clocks(sp);
reset_control_assert(sp->apb_rst);
unregister_pll_mux:
cdns_sierra_pll_mux_unregister(sp, dn);
@@ -1059,6 +1111,7 @@ static int cdns_sierra_phy_remove(struct platform_device *pdev)
reset_control_assert(phy->apb_rst);
pm_runtime_disable(&pdev->dev);
+ cdns_sierra_phy_disable_clocks(phy);
/*
* The device level resets will be put automatically.
* Need to put the subnode resets here though.
--
2.17.1
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