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Message-Id: <20201227130407.10991-3-wsa+renesas@sang-engineering.com>
Date: Sun, 27 Dec 2020 14:04:03 +0100
From: Wolfram Sang <wsa+renesas@...g-engineering.com>
To: linux-renesas-soc@...r.kernel.org
Cc: Wolfram Sang <wsa+renesas@...g-engineering.com>,
Geert Uytterhoeven <geert+renesas@...der.be>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>, linux-clk@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: [PATCH 2/5] clk: renesas: r8a779a0: add clocks for RAVB
Signed-off-by: Wolfram Sang <wsa+renesas@...g-engineering.com>
---
drivers/clk/renesas/r8a779a0-cpg-mssr.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/clk/renesas/r8a779a0-cpg-mssr.c b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
index 04514140e615..5be70a6a7904 100644
--- a/drivers/clk/renesas/r8a779a0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
@@ -148,6 +148,12 @@ static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = {
};
static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = {
+ DEF_MOD("avb0", 211, R8A779A0_CLK_S3D1),
+ DEF_MOD("avb1", 212, R8A779A0_CLK_S3D1),
+ DEF_MOD("avb2", 213, R8A779A0_CLK_S3D1),
+ DEF_MOD("avb3", 214, R8A779A0_CLK_S3D1),
+ DEF_MOD("avb4", 215, R8A779A0_CLK_S3D1),
+ DEF_MOD("avb5", 216, R8A779A0_CLK_S3D1),
DEF_MOD("csi40", 331, R8A779A0_CLK_CSI0),
DEF_MOD("csi41", 400, R8A779A0_CLK_CSI0),
DEF_MOD("csi42", 401, R8A779A0_CLK_CSI0),
--
2.29.2
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