linux-kernel - [PATCH 2/6] arm64: dts: renesas: falcon: add SCIF0 nodes

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Message-Id: <20201228112715.14947-3-wsa+renesas@sang-engineering.com>
Date:   Mon, 28 Dec 2020 12:27:09 +0100
From:   Wolfram Sang <wsa+renesas@...g-engineering.com>
To:     linux-renesas-soc@...r.kernel.org
Cc:     Wolfram Sang <wsa+renesas@...g-engineering.com>,
        Geert Uytterhoeven <geert+renesas@...der.be>,
        Magnus Damm <magnus.damm@...il.com>,
        Rob Herring <robh+dt@...nel.org>, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org
Subject: [PATCH 2/6] arm64: dts: renesas: falcon: add SCIF0 nodes

SCIF0 has been enabled by the firmware, so it worked already. Still, add
the proper nodes to make it work in any case.

Signed-off-by: Wolfram Sang <wsa+renesas@...g-engineering.com>
---
 .../boot/dts/renesas/r8a779a0-falcon.dts      | 25 +++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts b/arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts
index 0c44466d398f..54763c73dc74 100644
--- a/arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts
+++ b/arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts
@@ -205,6 +205,9 @@ &mmc0 {
 };
 
 &pfc {
+	pinctrl-0 = <&scif_clk_pins>;
+	pinctrl-names = "default";
+
 	avb0_pins: avb0 {
 		mux {
 			groups = "avb0_link", "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk";
@@ -348,9 +351,31 @@ mmc_pins: mmc {
 		function = "mmc";
 		power-source = <1800>;
 	};
+
+	scif0_pins: scif0 {
+		groups = "scif0_data", "scif0_ctrl";
+		function = "scif0";
+	};
+
+	scif_clk_pins: scif_clk {
+		groups = "scif_clk";
+		function = "scif_clk";
+	};
 };
 
 &rwdt {
 	timeout-sec = <60>;
 	status = "okay";
 };
+
+&scif0 {
+	pinctrl-0 = <&scif0_pins>;
+	pinctrl-names = "default";
+
+	uart-has-rtscts;
+	status = "okay";
+};
+
+&scif_clk {
+	clock-frequency = <24000000>;
+};
-- 
2.29.2