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Date:   Mon, 28 Dec 2020 10:59:39 +0800
From:   Qing Zhang <zhangqing@...ngson.cn>
To:     Mark Brown <broonie@...nel.org>, Rob Herring <robh+dt@...nel.org>,
        ThomasBogendoerfer <tsbogend@...ha.franken.de>
Cc:     linux-spi@...r.kernel.org, Huacai Chen <chenhc@...ote.com>,
        Jiaxun Yang <jiaxun.yang@...goat.com>, yangtiezhu@...ngson.cn,
        devicetree@...r.kernel.org, linux-mips@...r.kernel.org,
        linux-kernel@...r.kernel.org
Subject: [PATCH v6 2/4] spi: ls7a: Add YAML schemas

Switch the DT binding to a YAML schema to enable the DT validation.

Reviewed-by: Huacai Chen <chenhuacai@...nel.org>
Signed-off-by: Qing Zhang <zhangqing@...ngson.cn>
---

v4:
- fix warnings/errors about running 'make dt_binding_check'

v5:
- remove num-chipelects

v6:
- No changes

---
 .../devicetree/bindings/spi/loongson,spi-ls7a.yaml | 44 ++++++++++++++++++++++
 1 file changed, 44 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/spi/loongson,spi-ls7a.yaml

diff --git a/Documentation/devicetree/bindings/spi/loongson,spi-ls7a.yaml b/Documentation/devicetree/bindings/spi/loongson,spi-ls7a.yaml
new file mode 100644
index 0000000..b90b28b
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/loongson,spi-ls7a.yaml
@@ -0,0 +1,44 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spi/loongson,spi-ls7a.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Loongson LS7A PCH SPI Controller
+
+maintainers:
+  - Qing Zhang <zhangqing@...ngson.cn>
+
+description: |
+  This controller can be found in Loongson-3 systems with LS7A PCH.
+
+properties:
+  compatible:
+    const: loongson,ls7a-spi
+
+  reg:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    pci {
+        #address-cells = <3>;
+        #size-cells = <2>;
+
+        spi@16,0 {
+            compatible = "pci0014,7a0b.0",
+                             "pci0014,7a0b",
+                             "pciclass088000",
+                             "pciclass0800";
+
+            reg = <0xb000 0x0 0x0 0x0 0x0>;
+        };
+    };
+
+...
-- 
2.1.0

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