linux-kernel - Re: [PATCH v1 2/3] x86/cpu: Set low performance CRC32C flag on some Zhaoxin CPUs

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Message-ID: <607494aa-674a-fe93-50f6-2c45f385f7e9@intel.com>
Date:   Thu, 7 Jan 2021 07:52:49 -0800
From:   Dave Hansen <dave.hansen@...el.com>
To:     Tony W Wang-oc <TonyWWang-oc@...oxin.com>,
        herbert@...dor.apana.org.au, davem@...emloft.net,
        tglx@...utronix.de, mingo@...hat.com, bp@...en8.de, x86@...nel.org,
        hpa@...or.com, tony.luck@...el.com, seanjc@...gle.com,
        fenghua.yu@...el.com, thomas.lendacky@....com,
        kyung.min.park@...el.com, kim.phillips@....com,
        mgross@...ux.intel.com, peterz@...radead.org,
        krish.sadhukhan@...cle.com, liam.merwick@...cle.com,
        mlevitsk@...hat.com, reinette.chatre@...el.com, babu.moger@....com,
        linux-crypto@...r.kernel.org, linux-kernel@...r.kernel.org
Cc:     TimGuo-oc@...oxin.com, CooperYan@...oxin.com,
        QiyuanWang@...oxin.com, HerryYang@...oxin.com,
        CobeChen@...oxin.com, SilviaZhao@...oxin.com
Subject: Re: [PATCH v1 2/3] x86/cpu: Set low performance CRC32C flag on some
 Zhaoxin CPUs

On 1/6/21 10:19 PM, Tony W Wang-oc wrote:
> +	/*
> +	 * These CPUs declare support SSE4.2 instruction sets but
> +	 * having low performance CRC32C instruction implementation.
> +	 */
> +	if (c->x86 == 0x6 || (c->x86 == 0x7 && c->x86_model <= 0x3b))
> +		set_cpu_cap(c, X86_FEATURE_CRC32C);
>  }

On the Intel side, we've tried to move away from open-coded model
numbers.  Say another CPU is released that has a microarchitecture close
to 0x3b, but has a model of 0x3c.  It's a *LOT* easier to grep for
INTEL_FAM6_NEHALEM (or whatever) than 0x3c.  See:

	arch/x86/include/asm/intel-family.h

for examples.