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Date: Mon, 11 Jan 2021 18:51:59 +0800 From: Tony W Wang-oc <TonyWWang-oc@...oxin.com> To: Borislav Petkov <bp@...en8.de> CC: <herbert@...dor.apana.org.au>, <davem@...emloft.net>, <tglx@...utronix.de>, <mingo@...hat.com>, <x86@...nel.org>, <hpa@...or.com>, <tony.luck@...el.com>, <dave.hansen@...el.com>, <seanjc@...gle.com>, <fenghua.yu@...el.com>, <thomas.lendacky@....com>, <kyung.min.park@...el.com>, <kim.phillips@....com>, <mgross@...ux.intel.com>, <peterz@...radead.org>, <krish.sadhukhan@...cle.com>, <liam.merwick@...cle.com>, <mlevitsk@...hat.com>, <reinette.chatre@...el.com>, <babu.moger@....com>, <linux-crypto@...r.kernel.org>, <linux-kernel@...r.kernel.org>, <TimGuo-oc@...oxin.com>, <CooperYan@...oxin.com>, <QiyuanWang@...oxin.com>, <HerryYang@...oxin.com>, <CobeChen@...oxin.com>, <SilviaZhao@...oxin.com> Subject: Re: [PATCH v1 1/3] x86/cpufeatures: Add low performance CRC32C instruction CPU feature On 07/01/2021 14:37, Borislav Petkov wrote: > On Thu, Jan 07, 2021 at 02:19:06PM +0800, Tony W Wang-oc wrote: >> SSE4.2 on Zhaoxin CPUs are compatible with Intel. The presence of >> CRC32C instruction is enumerated by CPUID.01H:ECX.SSE4_2[bit 20] = 1. >> Some Zhaoxin CPUs declare support SSE4.2 instruction sets but their >> CRC32C instruction are working with low performance. >> >> Add a synthetic CPU flag to indicates that the CRC32C instruction is >> not working as intended. This low performance CRC32C instruction flag >> is depend on X86_FEATURE_XMM4_2. >> >> Signed-off-by: Tony W Wang-oc <TonyWWang-oc@...oxin.com> >> --- >> arch/x86/include/asm/cpufeatures.h | 1 + >> arch/x86/kernel/cpu/cpuid-deps.c | 1 + >> 2 files changed, 2 insertions(+) >> >> diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h >> index 84b8878..9e8151b 100644 >> --- a/arch/x86/include/asm/cpufeatures.h >> +++ b/arch/x86/include/asm/cpufeatures.h >> @@ -292,6 +292,7 @@ >> #define X86_FEATURE_FENCE_SWAPGS_KERNEL (11*32+ 5) /* "" LFENCE in kernel entry SWAPGS path */ >> #define X86_FEATURE_SPLIT_LOCK_DETECT (11*32+ 6) /* #AC for split lock */ >> #define X86_FEATURE_PER_THREAD_MBA (11*32+ 7) /* "" Per-thread Memory Bandwidth Allocation */ >> +#define X86_FEATURE_CRC32C (11*32+ 8) /* "" Low performance CRC32C instruction */ > > Didn't hpa say to create a BUG flag for it - X86_BUG...? Low performance > insn sounds like a bug and not a feature to me. > > And call it X86_BUG_CRC32C_SLOW or ..._UNUSABLE to denote what it means. > This issue will be enhanced by hardware and patch submit will be pending. Sincerely Tonyw
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