lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
Open Source and information security mailing list archives
| ||
|
Date: Fri, 8 Jan 2021 11:46:05 +0100 From: Peter Rosin <peda@...ntia.se> To: Kishon Vijay Abraham I <kishon@...com>, Vinod Koul <vkoul@...nel.org>, Rob Herring <robh+dt@...nel.org>, Nishanth Menon <nm@...com>, Swapnil Jakhade <sjakhade@...ence.com> Cc: linux-kernel@...r.kernel.org, devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org Subject: Re: [PATCH 4/7] dt-bindings: ti-serdes-mux: Add defines for AM64 SoC Hi! On 2020-12-24 12:42, Kishon Vijay Abraham I wrote: > AM64 has a single lane SERDES which can be configured to be used > with either PCIe or USB. Define the possilbe values for the SERDES > function in AM64 SoC here. > > Signed-off-by: Kishon Vijay Abraham I <kishon@...com> > --- > include/dt-bindings/mux/ti-serdes.h | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/include/dt-bindings/mux/ti-serdes.h b/include/dt-bindings/mux/ti-serdes.h > index 9047ec6bd3cf..68e0f76deed1 100644 > --- a/include/dt-bindings/mux/ti-serdes.h > +++ b/include/dt-bindings/mux/ti-serdes.h > @@ -90,4 +90,8 @@ > #define J7200_SERDES0_LANE3_USB 0x2 > #define J7200_SERDES0_LANE3_IP4_UNUSED 0x3 > > +/* AM64 */ In case you end up keeping these defines, despite the comment by Rob... Nitpick, the J721E and J7200 sections have a blank line here, between the header comment and the actual defines. But mehh... Acked-by: Peter Rosin <peda@...ntia.se> Cheers, Peter > +#define AM64_SERDES0_LANE0_PCIE0 0x0 > +#define AM64_SERDES0_LANE0_USB 0x1 > + > #endif /* _DT_BINDINGS_MUX_TI_SERDES */ >
Powered by blists - more mailing lists