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Date:   Fri, 8 Jan 2021 16:44:48 +0530
From:   Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
To:     Konrad Dybcio <konrad.dybcio@...ainline.org>
Cc:     mturquette@...libre.com, sboyd@...nel.org, robh+dt@...nel.org,
        jassisinghbrar@...il.com, viresh.kumar@...aro.org,
        ulf.hansson@...aro.org, bjorn.andersson@...aro.org,
        agross@...nel.org, linux-arm-msm@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-clk@...r.kernel.org,
        devicetree@...r.kernel.org
Subject: Re: [PATCH 4/5] clk: qcom: Add A7 PLL support

On Mon, Jan 04, 2021 at 04:30:11PM +0100, Konrad Dybcio wrote:
> Hi,
> 
> could you explicitly state in the probe function (or just in the driver in general, as there's not much more?) and the config structs that the target SoC is X55?
> 

The compatible says it...

> A few more SoCs (MDM9607, MSM8x26 and some others) also use what's known as "A7PLL" downstream, but all of them have a separate configuration for their specific PLLs, which aren't compatible with each other.
> 

Yes, but that difference can be factored using the SoC specific compatibles in
future. The idea here is to have a generic A7 PLL driver much like A53 one and
use SoC specific PLL settings.

Thanks,
Mani

> 
> Konrad
> 

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