linux-kernel - [PATCH] drivers/tty: Use bitwise instead of arithmetic operator for flags

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Message-Id: <1610705031-20332-1-git-send-email-abaci-bugfix@linux.alibaba.com>
Date:   Fri, 15 Jan 2021 18:03:51 +0800
From:   Jiapeng Zhong <abaci-bugfix@...ux.alibaba.com>
To:     gregkh@...uxfoundation.org
Cc:     jirislaby@...nel.org, linux-kernel@...r.kernel.org,
        Jiapeng Zhong <abaci-bugfix@...ux.alibaba.com>
Subject: [PATCH] drivers/tty: Use bitwise instead of arithmetic operator for flags

Fix the following coccicheck warning:

./drivers/tty/synclink_gt.c:4384:15-16: WARNING: sum of probable
bitmasks, consider |
./drivers/tty/synclink_gt.c:4342:39-40: WARNING: sum of probable
bitmasks, consider |
./drivers/tty/synclink_gt.c:4280:48-49: WARNING: sum of probable
bitmasks, consider |
./drivers/tty/synclink_gt.c:2221:20-21: WARNING: sum of probable
bitmasks, consider |

Reported-by: Abaci Robot <abaci@...ux.alibaba.com>
Signed-off-by: Jiapeng Zhong <abaci-bugfix@...ux.alibaba.com>
---
 drivers/tty/synclink_gt.c | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/drivers/tty/synclink_gt.c b/drivers/tty/synclink_gt.c
index c0b384e..d302c08 100644
--- a/drivers/tty/synclink_gt.c
+++ b/drivers/tty/synclink_gt.c
@@ -2219,7 +2219,7 @@ static void isr_tdma(struct slgt_info *info)
 	 */
 	wr_reg32(info, TDCSR, status);	/* clear pending */
 
-	if (status & (BIT5 + BIT4 + BIT3)) {
+	if (status & (BIT5 | BIT4 | BIT3)) {
 		// another transmit buffer has completed
 		// run bottom half to get more send data from user
 		info->pending_bh |= BH_TRANSMIT;
@@ -4265,7 +4265,9 @@ static void sync_mode(struct slgt_info *info)
 	case MGSL_MODE_XSYNC:
 		val |= BIT15 + BIT13;
 		break;
-	case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
+	case MGSL_MODE_MONOSYNC:
+		val |= BIT14 | BIT13;
+		break;
 	case MGSL_MODE_BISYNC:   val |= BIT15; break;
 	case MGSL_MODE_RAW:      val |= BIT13; break;
 	}
@@ -4278,7 +4280,9 @@ static void sync_mode(struct slgt_info *info)
 	case HDLC_ENCODING_NRZI_MARK:     val |= BIT11; break;
 	case HDLC_ENCODING_NRZI:          val |= BIT11 + BIT10; break;
 	case HDLC_ENCODING_BIPHASE_MARK:  val |= BIT12; break;
-	case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
+	case HDLC_ENCODING_BIPHASE_SPACE:
+		val |= BIT12 | BIT10;
+		break;
 	case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
 	case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
 	}
@@ -4382,7 +4386,7 @@ static void sync_mode(struct slgt_info *info)
 		// reference clock, so take TxC from BRG/16 to get
 		// transmit clock at actual data rate
 		if (info->params.flags & HDLC_FLAG_RXC_DPLL)
-			val |= BIT6 + BIT5;	/* 011, txclk = BRG/16 */
+			val |= BIT6 | BIT5;	/* 011, txclk = BRG/16 */
 		else
 			val |= BIT6;	/* 010, txclk = BRG */
 	}
-- 
1.8.3.1