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Date: Tue, 19 Jan 2021 11:20:48 +0800 From: DENG Qingfang <dqfext@...il.com> To: Linus Walleij <linus.walleij@...aro.org> Cc: Andrew Lunn <andrew@...n.ch>, Vivien Didelot <vivien.didelot@...il.com>, Florian Fainelli <f.fainelli@...il.com>, Vladimir Oltean <olteanv@...il.com>, "David S. Miller" <davem@...emloft.net>, Jakub Kicinski <kuba@...nel.org>, Rob Herring <robh+dt@...nel.org>, Matthias Brugger <matthias.bgg@...il.com>, Sean Wang <sean.wang@...iatek.com>, Landen Chao <Landen.Chao@...iatek.com>, Philipp Zabel <p.zabel@...gutronix.de>, Russell King <linux@...linux.org.uk>, netdev <netdev@...r.kernel.org>, "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" <devicetree@...r.kernel.org>, Linux ARM <linux-arm-kernel@...ts.infradead.org>, "moderated list:ARM/Mediatek SoC support" <linux-mediatek@...ts.infradead.org>, "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>, René van Dorst <opensource@...rst.com>, Frank Wunderlich <frank-w@...lic-files.de> Subject: Re: [PATCH net-next 2/2] drivers: net: dsa: mt7530: MT7530 optional GPIO support Hi Linus, On Mon, Jan 18, 2021 at 10:55 PM Linus Walleij <linus.walleij@...aro.org> wrote: > > So for offset 0..14 this becomes bits > 0, 1, 2, 4, 5, 6, 8, 9, 10, 12 ... 18 > > What is the logic in this and is it what you intend? Yes. Bit 0..2 are phy 0's LED 0..2, bit 4..6 are phy 1's LED 0..2, etc. > Please add a comment explaining what the offset is supposed > to become for offsets 0..14 and why. I already added to mt7530.h, perhaps I should copy it here? > > > + gc->ngpio = 15; > > And it really IS 15 not 16? Not that I know network equipment > very well... Yes, 3 LEDs for each phy. > > Yours, > Linus Walleij
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