linux-kernel - [PATCH 4/6] MIPS: Octeon: qspinlock: Exclude mmiowb()

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Message-Id: <20210127203627.47510-5-alexander.sverdlin@nokia.com>
Date:   Wed, 27 Jan 2021 21:36:25 +0100
From:   Alexander A Sverdlin <alexander.sverdlin@...ia.com>
To:     Paul Burton <paul.burton@...tec.com>, linux-mips@...r.kernel.org
Cc:     Alexander Sverdlin <alexander.sverdlin@...ia.com>,
        Thomas Bogendoerfer <tsbogend@...ha.franken.de>,
        Will Deacon <will@...nel.org>,
        Peter Zijlstra <peterz@...radead.org>,
        Boqun Feng <boqun.feng@...il.com>,
        Ingo Molnar <mingo@...hat.com>, linux-kernel@...r.kernel.org
Subject: [PATCH 4/6] MIPS: Octeon: qspinlock: Exclude mmiowb()

From: Alexander Sverdlin <alexander.sverdlin@...ia.com>

On Octeon mmiowb() is SYNCW, which is already contained in
smp_store_release(). Removing superfluous barrier brings around 10%
performance on uncontended tight spinlock loops.

Signed-off-by: Alexander Sverdlin <alexander.sverdlin@...ia.com>
---
 arch/mips/include/asm/spinlock.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/mips/include/asm/spinlock.h b/arch/mips/include/asm/spinlock.h
index 0a707f3..fbe97b4 100644
--- a/arch/mips/include/asm/spinlock.h
+++ b/arch/mips/include/asm/spinlock.h
@@ -21,8 +21,10 @@
  */
 static inline void queued_spin_unlock(struct qspinlock *lock)
 {
+#ifndef CONFIG_CPU_CAVIUM_OCTEON
 	/* This could be optimised with ARCH_HAS_MMIOWB */
 	mmiowb();
+#endif
 	smp_store_release(&lock->locked, 0);
 #ifdef CONFIG_CPU_CAVIUM_OCTEON
 	nudge_writes();
-- 
2.10.2