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Date: Sun, 31 Jan 2021 11:39:46 +0800 From: Chun-Kuang Hu <chunkuang.hu@...nel.org> To: Hsin-Yi Wang <hsinyi@...omium.org> Cc: CK Hu <ck.hu@...iatek.com>, Philipp Zabel <p.zabel@...gutronix.de>, Matthias Brugger <matthias.bgg@...il.com>, Mark Rutland <mark.rutland@....com>, DTML <devicetree@...r.kernel.org>, Yongqiang Niu <yongqiang.niu@...iatek.com>, David Airlie <airlied@...ux.ie>, linux-kernel <linux-kernel@...r.kernel.org>, DRI Development <dri-devel@...ts.freedesktop.org>, "moderated list:ARM/Mediatek SoC support" <linux-mediatek@...ts.infradead.org>, Daniel Vetter <daniel@...ll.ch>, Linux ARM <linux-arm-kernel@...ts.infradead.org> Subject: Re: [PATCH v13 6/8] drm/mediatek: enable dither function Hi, Hsin-Yi: Hsin-Yi Wang <hsinyi@...omium.org> 於 2021年1月29日 週五 下午5:23寫道: > > From: Yongqiang Niu <yongqiang.niu@...iatek.com> > > Enable dither function to improve the display quality for dither > supported bpc 4, 6, 8. For not supported bpc, use relay mode. > > Signed-off-by: Yongqiang Niu <yongqiang.niu@...iatek.com> > Signed-off-by: Hsin-Yi Wang <hsinyi@...omium.org> > --- > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 15 ++++++++++++--- > 1 file changed, 12 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > index ac2cb25620357..5761dd15eedf2 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > @@ -53,6 +53,7 @@ > #define DITHER_EN BIT(0) > #define DISP_DITHER_CFG 0x0020 > #define DITHER_RELAY_MODE BIT(0) > +#define DITHER_ENGINE_EN BIT(1) > #define DISP_DITHER_SIZE 0x0030 > > #define LUT_10BIT_MASK 0x03ff > @@ -314,9 +315,17 @@ static void mtk_dither_config(struct device *dev, unsigned int w, > unsigned int bpc, struct cmdq_pkt *cmdq_pkt) > { > struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > - > - mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_DITHER_SIZE); > - mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG); > + bool valid_bpc = (bpc == 4 || bpc == 6 || bpc == 8); > + > + mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, > + DISP_DITHER_SIZE); > + if (valid_bpc) > + mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc, > + DISP_DITHER_CFG, DITHER_ENGINE_EN, > + cmdq_pkt); > + else > + mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, > + priv->regs, DISP_DITHER_CFG); od has relay mode, static void mtk_od_config(struct mtk_ddp_comp *comp, unsigned int w, unsigned int h, unsigned int vrefresh, unsigned int bpc, struct cmdq_pkt *cmdq_pkt) { mtk_ddp_write(cmdq_pkt, w << 16 | h, comp, DISP_OD_SIZE); mtk_ddp_write(cmdq_pkt, OD_RELAYMODE, comp, DISP_OD_CFG); mtk_dither_set(comp, bpc, DISP_OD_CFG, cmdq_pkt); } and it does not check valid bpc (I think drm core already set bpc to 4, 6, 8 or 0), so align implementation of mtk_dither_config() with mtk_od_config(). gamma also has relay mode (refer to [1] page 689), but we need to enable gamma's gamma function, so we do not set gamma to relay mode. So I think maybe we could implement mtk_dither_config() as: mtk_dither_config() { mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_DITHER_SIZE); mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG); mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc, DISP_DITHER_CFG, DITHER_ENGINE_EN, cmdq_pkt); } [1] https://www.96boards.org/documentation/consumer/mediatekx20/additional-docs/docs/MT6797_Register_Table_Part_2.pdf Regards, Chun-Kuang. > } > > static void mtk_dither_start(struct device *dev) > -- > 2.30.0.365.g02bc693789-goog > > > _______________________________________________ > Linux-mediatek mailing list > Linux-mediatek@...ts.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-mediatek
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