linux-kernel - RE: [EXT] Re: [PATCH 03/11] dts: mvebu: Add pin control definitions for SDIO interafce

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Message-ID: <DM5PR18MB1452ABE0F98B38A86DCEE406CAB49@DM5PR18MB1452.namprd18.prod.outlook.com>
Date:   Wed, 3 Feb 2021 14:39:57 +0000
From:   Kostya Porotchkin <kostap@...vell.com>
To:     Baruch Siach <baruch@...s.co.il>
CC:     "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "andrew@...n.ch" <andrew@...n.ch>,
        "jaz@...ihalf.com" <jaz@...ihalf.com>,
        "gregory.clement@...tlin.com" <gregory.clement@...tlin.com>,
        "linux@...linux.org.uk" <linux@...linux.org.uk>,
        Nadav Haklai <nadavh@...vell.com>,
        "robh+dt@...nel.org" <robh+dt@...nel.org>,
        "Stefan Chulski" <stefanc@...vell.com>,
        "mw@...ihalf.com" <mw@...ihalf.com>,
        "Ben Peled" <bpeled@...vell.com>,
        "sebastian.hesselbarth@...il.com" <sebastian.hesselbarth@...il.com>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>
Subject: RE: [EXT] Re: [PATCH 03/11] dts: mvebu: Add pin control definitions
 for SDIO interafce



> -----Original Message-----
> From: Baruch Siach <baruch@...s.co.il>
> Sent: Wednesday, February 3, 2021 16:01
> To: Kostya Porotchkin <kostap@...vell.com>
> Cc: linux-kernel@...r.kernel.org; devicetree@...r.kernel.org;
> andrew@...n.ch; jaz@...ihalf.com; gregory.clement@...tlin.com;
> linux@...linux.org.uk; Nadav Haklai <nadavh@...vell.com>;
> robh+dt@...nel.org; Stefan Chulski <stefanc@...vell.com>;
> mw@...ihalf.com; Ben Peled <bpeled@...vell.com>;
> sebastian.hesselbarth@...il.com; linux-arm-kernel@...ts.infradead.org
> Subject: [EXT] Re: [PATCH 03/11] dts: mvebu: Add pin control definitions for
> SDIO interafce
> 
> External Email
> 
> ----------------------------------------------------------------------
> Hi Konstantin,
> 
> On Wed, Feb 03 2021, kostap@...vell.com wrote:
> > From: Konstantin Porotchkin <kostap@...vell.com>
> >
> > Add SDIO mode pin control configration for CP0 on A8K DB.
> 
> This patch does not touch the A8K DB device-tree file.
> 
[KP] Right, it changes the SoC DTSI. I missed it when ported the patch.
Will fix in the next version

Kosta

> baruch
> 
> >
> > Signed-off-by: Konstantin Porotchkin <kostap@...vell.com>
> > ---
> >  arch/arm64/boot/dts/marvell/armada-70x0.dtsi | 6 ++++++
> > arch/arm64/boot/dts/marvell/armada-80x0.dtsi | 6 ++++++
> >  2 files changed, 12 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
> > b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
> > index 293403a1a333..179218774ba9 100644
> > --- a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
> > +++ b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
> > @@ -47,6 +47,12 @@
> >  	cp0_pinctrl: pinctrl {
> >  		compatible = "marvell,armada-7k-pinctrl";
> >
> > +		sdhci_pins: sdhi-pins {
> > +			marvell,pins = "mpp56", "mpp57", "mpp58",
> > +				       "mpp59", "mpp60", "mpp61", "mpp62";
> > +			marvell,function = "sdio";
> > +		};
> > +
> >  		nand_pins: nand-pins {
> >  			marvell,pins =
> >  			"mpp15", "mpp16", "mpp17", "mpp18", diff --git
> > a/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
> > b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
> > index ee67c70bf02e..64100ae204da 100644
> > --- a/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
> > +++ b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
> > @@ -70,6 +70,12 @@
> >  &cp0_syscon0 {
> >  	cp0_pinctrl: pinctrl {
> >  		compatible = "marvell,armada-8k-cpm-pinctrl";
> > +
> > +		sdhci_pins: sdhi-pins {
> > +			marvell,pins = "mpp56", "mpp57", "mpp58",
> > +				       "mpp59", "mpp60", "mpp61", "mpp62";
> > +			marvell,function = "sdio";
> > +		};
> >  	};
> >  };
> 
> 
> --
>                                                      ~. .~   Tk Open Systems
> =}------------------------------------------------ooO--U--Ooo------------{=
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