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Message-ID: <CAPv3WKc4WMnwQ0K_bQhBYmRvLkDCC-CXD5gCd-PdnjzxKdhruQ@mail.gmail.com>
Date: Thu, 4 Feb 2021 20:00:01 +0100
From: Marcin Wojtas <mw@...ihalf.com>
To: Stefan Chulski <stefanc@...vell.com>
Cc: netdev <netdev@...r.kernel.org>,
Thomas Petazzoni <thomas.petazzoni@...tlin.com>,
"David S. Miller" <davem@...emloft.net>, nadavh@...vell.com,
Yan Markman <ymarkman@...vell.com>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
Jakub Kicinski <kuba@...nel.org>,
Russell King - ARM Linux <linux@...linux.org.uk>,
Andrew Lunn <andrew@...n.ch>,
Russell King <rmk+kernel@...linux.org.uk>, atenart@...nel.org
Subject: Re: [PATCH v7 net-next 05/15] net: mvpp2: always compare hw-version
vs MVPP21
Hi,
wt., 2 lut 2021 o 09:17 <stefanc@...vell.com> napisał(a):
>
> From: Stefan Chulski <stefanc@...vell.com>
>
> Currently we have PP2v1 and PP2v2 hw-versions, with some different
> handlers depending upon condition hw_version = MVPP21/MVPP22.
> In a future there will be also PP2v3. Let's use now the generic
> "if equal/notEqual MVPP21" for all cases instead of "if MVPP22".
>
> This patch does not change any functionality.
> It is not intended to introduce PP2v3.
This is a preparation patch and it should be commited before "net:
mvpp2: add PPv23 version definition"
Thanks,
Marcin
> It just modifies MVPP21/MVPP22 check-condition
> bringing it to generic and unified form correct for new-code
> introducing and PP2v3 net-next generation.
>
> Signed-off-by: Stefan Chulski <stefanc@...vell.com>
> ---
> drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 36 ++++++++++----------
> 1 file changed, 18 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
> index 11c56d2..d80947a 100644
> --- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
> +++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
> @@ -320,7 +320,7 @@ static int mvpp2_get_nrxqs(struct mvpp2 *priv)
> {
> unsigned int nrxqs;
>
> - if (priv->hw_version == MVPP22 && queue_mode == MVPP2_QDIST_SINGLE_MODE)
> + if (priv->hw_version != MVPP21 && queue_mode == MVPP2_QDIST_SINGLE_MODE)
> return 1;
>
> /* According to the PPv2.2 datasheet and our experiments on
> @@ -447,7 +447,7 @@ static void mvpp2_bm_bufs_get_addrs(struct device *dev, struct mvpp2 *priv,
> MVPP2_BM_PHY_ALLOC_REG(bm_pool->id));
> *phys_addr = mvpp2_thread_read(priv, thread, MVPP2_BM_VIRT_ALLOC_REG);
>
> - if (priv->hw_version == MVPP22) {
> + if (priv->hw_version != MVPP21) {
> u32 val;
> u32 dma_addr_highbits, phys_addr_highbits;
>
> @@ -743,7 +743,7 @@ static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool,
> if (test_bit(thread, &port->priv->lock_map))
> spin_lock_irqsave(&port->bm_lock[thread], flags);
>
> - if (port->priv->hw_version == MVPP22) {
> + if (port->priv->hw_version != MVPP21) {
> u32 val = 0;
>
> if (sizeof(dma_addr_t) == 8)
> @@ -1200,7 +1200,7 @@ static bool mvpp2_port_supports_xlg(struct mvpp2_port *port)
>
> static bool mvpp2_port_supports_rgmii(struct mvpp2_port *port)
> {
> - return !(port->priv->hw_version == MVPP22 && port->gop_id == 0);
> + return !(port->priv->hw_version != MVPP21 && port->gop_id == 0);
> }
>
> /* Port configuration routines */
> @@ -1818,7 +1818,7 @@ static void mvpp2_mac_reset_assert(struct mvpp2_port *port)
> MVPP2_GMAC_PORT_RESET_MASK;
> writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
>
> - if (port->priv->hw_version == MVPP22 && port->gop_id == 0) {
> + if (port->priv->hw_version != MVPP21 && port->gop_id == 0) {
> val = readl(port->base + MVPP22_XLG_CTRL0_REG) &
> ~MVPP22_XLG_CTRL0_MAC_RESET_DIS;
> writel(val, port->base + MVPP22_XLG_CTRL0_REG);
> @@ -1831,7 +1831,7 @@ static void mvpp22_pcs_reset_assert(struct mvpp2_port *port)
> void __iomem *mpcs, *xpcs;
> u32 val;
>
> - if (port->priv->hw_version != MVPP22 || port->gop_id != 0)
> + if (port->priv->hw_version == MVPP21 || port->gop_id != 0)
> return;
>
> mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id);
> @@ -1852,7 +1852,7 @@ static void mvpp22_pcs_reset_deassert(struct mvpp2_port *port)
> void __iomem *mpcs, *xpcs;
> u32 val;
>
> - if (port->priv->hw_version != MVPP22 || port->gop_id != 0)
> + if (port->priv->hw_version == MVPP21 || port->gop_id != 0)
> return;
>
> mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id);
> @@ -4189,7 +4189,7 @@ static void mvpp2_start_dev(struct mvpp2_port *port)
> /* Enable interrupts on all threads */
> mvpp2_interrupts_enable(port);
>
> - if (port->priv->hw_version == MVPP22)
> + if (port->priv->hw_version != MVPP21)
> mvpp22_mode_reconfigure(port);
>
> if (port->phylink) {
> @@ -4405,7 +4405,7 @@ static int mvpp2_open(struct net_device *dev)
> valid = true;
> }
>
> - if (priv->hw_version == MVPP22 && port->port_irq) {
> + if (priv->hw_version != MVPP21 && port->port_irq) {
> err = request_irq(port->port_irq, mvpp2_port_isr, 0,
> dev->name, port);
> if (err) {
> @@ -6053,7 +6053,7 @@ static int mvpp2__mac_prepare(struct phylink_config *config, unsigned int mode,
> MVPP2_GMAC_PORT_RESET_MASK,
> MVPP2_GMAC_PORT_RESET_MASK);
>
> - if (port->priv->hw_version == MVPP22) {
> + if (port->priv->hw_version != MVPP21) {
> mvpp22_gop_mask_irq(port);
>
> phy_power_off(port->comphy);
> @@ -6107,7 +6107,7 @@ static int mvpp2_mac_finish(struct phylink_config *config, unsigned int mode,
> {
> struct mvpp2_port *port = mvpp2_phylink_to_port(config);
>
> - if (port->priv->hw_version == MVPP22 &&
> + if (port->priv->hw_version != MVPP21 &&
> port->phy_interface != interface) {
> port->phy_interface = interface;
>
> @@ -6787,7 +6787,7 @@ static int mvpp2_init(struct platform_device *pdev, struct mvpp2 *priv)
> if (dram_target_info)
> mvpp2_conf_mbus_windows(dram_target_info, priv);
>
> - if (priv->hw_version == MVPP22)
> + if (priv->hw_version != MVPP21)
> mvpp2_axi_init(priv);
>
> /* Disable HW PHY polling */
> @@ -6950,7 +6950,7 @@ static int mvpp2_probe(struct platform_device *pdev)
> dev_warn(&pdev->dev, "Fail to alloc CM3 SRAM\n");
> }
>
> - if (priv->hw_version == MVPP22 && dev_of_node(&pdev->dev)) {
> + if (priv->hw_version != MVPP21 && dev_of_node(&pdev->dev)) {
> priv->sysctrl_base =
> syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
> "marvell,system-controller");
> @@ -6963,7 +6963,7 @@ static int mvpp2_probe(struct platform_device *pdev)
> priv->sysctrl_base = NULL;
> }
>
> - if (priv->hw_version == MVPP22 &&
> + if (priv->hw_version != MVPP21 &&
> mvpp2_get_nrxqs(priv) * 2 <= MVPP2_BM_MAX_POOLS)
> priv->percpu_pools = 1;
>
> @@ -7010,7 +7010,7 @@ static int mvpp2_probe(struct platform_device *pdev)
> if (err < 0)
> goto err_pp_clk;
>
> - if (priv->hw_version == MVPP22) {
> + if (priv->hw_version != MVPP21) {
> priv->mg_clk = devm_clk_get(&pdev->dev, "mg_clk");
> if (IS_ERR(priv->mg_clk)) {
> err = PTR_ERR(priv->mg_clk);
> @@ -7051,7 +7051,7 @@ static int mvpp2_probe(struct platform_device *pdev)
> return -EINVAL;
> }
>
> - if (priv->hw_version == MVPP22) {
> + if (priv->hw_version != MVPP21) {
> err = dma_set_mask(&pdev->dev, MVPP2_DESC_DMA_MASK);
> if (err)
> goto err_axi_clk;
> @@ -7131,10 +7131,10 @@ static int mvpp2_probe(struct platform_device *pdev)
> clk_disable_unprepare(priv->axi_clk);
>
> err_mg_core_clk:
> - if (priv->hw_version == MVPP22)
> + if (priv->hw_version != MVPP21)
> clk_disable_unprepare(priv->mg_core_clk);
> err_mg_clk:
> - if (priv->hw_version == MVPP22)
> + if (priv->hw_version != MVPP21)
> clk_disable_unprepare(priv->mg_clk);
> err_gop_clk:
> clk_disable_unprepare(priv->gop_clk);
> --
> 1.9.1
>
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