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Message-ID: <161280641307.76967.2250055755142713206@swboyd.mtv.corp.google.com>
Date: Mon, 08 Feb 2021 09:46:53 -0800
From: Stephen Boyd <sboyd@...nel.org>
To: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>,
jassisinghbrar@...il.com, mturquette@...libre.com,
robh+dt@...nel.org
Cc: viresh.kumar@...aro.org, ulf.hansson@...aro.org,
bjorn.andersson@...aro.org, agross@...nel.org,
linux-arm-msm@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-clk@...r.kernel.org, devicetree@...r.kernel.org,
Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
Subject: Re: [PATCH v3 3/5] dt-bindings: clock: Add Qualcomm A7 PLL binding
Quoting Manivannan Sadhasivam (2021-01-17 20:11:54)
> Add devicetree YAML binding for Cortex A7 PLL clock in Qualcomm
> platforms like SDX55.
>
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
> ---
Applied to clk-next
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