[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <161280637168.76967.9168707371952675235@swboyd.mtv.corp.google.com>
Date: Mon, 08 Feb 2021 09:46:11 -0800
From: Stephen Boyd <sboyd@...nel.org>
To: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>,
jassisinghbrar@...il.com, mturquette@...libre.com,
robh+dt@...nel.org
Cc: viresh.kumar@...aro.org, ulf.hansson@...aro.org,
bjorn.andersson@...aro.org, agross@...nel.org,
linux-arm-msm@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-clk@...r.kernel.org, devicetree@...r.kernel.org,
Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
Subject: Re: [PATCH v3 0/5] Add APCS support for SDX55
Quoting Manivannan Sadhasivam (2021-01-17 20:11:51)
> Changes in v2:
>
> * Modified the max_register value as per the SDX55 IPC offset in mailbox
> driver.
>
> Manivannan Sadhasivam (5):
> dt-bindings: mailbox: Add binding for SDX55 APCS
> mailbox: qcom: Add support for SDX55 APCS IPC
I think I can apply the clk patches to clk tree without the mailbox
patches, right?
> dt-bindings: clock: Add Qualcomm A7 PLL binding
> clk: qcom: Add A7 PLL support
> clk: qcom: Add SDX55 APCS clock controller support
>
Powered by blists - more mailing lists