linux-kernel - Re: [PATCH v3 5/5] clk: qcom: Add SDX55 APCS clock controller support

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Message-ID: <161280642697.76967.2863036519515305315@swboyd.mtv.corp.google.com>
Date:   Mon, 08 Feb 2021 09:47:06 -0800
From:   Stephen Boyd <sboyd@...nel.org>
To:     Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>,
        jassisinghbrar@...il.com, mturquette@...libre.com,
        robh+dt@...nel.org
Cc:     viresh.kumar@...aro.org, ulf.hansson@...aro.org,
        bjorn.andersson@...aro.org, agross@...nel.org,
        linux-arm-msm@...r.kernel.org, linux-kernel@...r.kernel.org,
        linux-clk@...r.kernel.org, devicetree@...r.kernel.org,
        Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
Subject: Re: [PATCH v3 5/5] clk: qcom: Add SDX55 APCS clock controller support

Quoting Manivannan Sadhasivam (2021-01-17 20:11:56)
> Add a driver for the SDX55 APCS clock controller. It is part of the APCS
> hardware block, which among other things implements also a combined mux
> and half integer divider functionality. The APCS clock controller has 3
> parent clocks:
> 
> 1. Board XO
> 2. Fixed rate GPLL0
> 3. A7 PLL
> 
> This is required for enabling CPU frequency scaling on SDX55-based
> platforms.
> 
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
> ---

Applied to clk-next