[<prev] [next>] [thread-next>] [day] [month] [year] [list]
Message-Id: <20210208114538.134766-1-taehyun.cho@samsung.com>
Date: Mon, 8 Feb 2021 20:45:38 +0900
From: taehyun cho <taehyun.cho@...sung.com>
To: balbi@...nel.org
Cc: taehyun.cho@...sung.com,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
linux-usb@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: [PATCH] usb: dwc3: make USB_DWC3_EXYNOS independent
'ARCH_EXYNOS' is no more used. 'USB_DWC3_EXYNOS' is glue layer
which can be used with Synopsys DWC3 controller on Exynos SoCs.
'USB_DWC3_EXYNOS' can be used from Exynos5 to Exynos9.
Signed-off-by: taehyun cho <taehyun.cho@...sung.com>
---
drivers/usb/dwc3/Kconfig | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig
index 2133acf8ee69..dc2f92ac8ef6 100644
--- a/drivers/usb/dwc3/Kconfig
+++ b/drivers/usb/dwc3/Kconfig
@@ -67,10 +67,10 @@ config USB_DWC3_OMAP
config USB_DWC3_EXYNOS
tristate "Samsung Exynos Platform"
- depends on (ARCH_EXYNOS || COMPILE_TEST) && OF
+ depends on (USB_DWC3 || COMPILE_TEST) && OF
default USB_DWC3
help
- Recent Exynos5 SoCs ship with one DesignWare Core USB3 IP inside,
+ Exynos SoCs chip with one DesignWare Core USB3 IP inside,
say 'Y' or 'M' if you have one such device.
config USB_DWC3_PCI
--
2.26.0
Powered by blists - more mailing lists